8
LT1711/LT1712
latch when a flow-through condition is desired. The latch
pin is designed to be driven with either a TTL or CMOS
output. It has built-in hysteresis of approximately 100mV,
so that slow moving or noisy input signals do not impact
latch performance.
For the LT1712, if only one of the comparators is being
used at a given time, it is best to latch the second compara-
tor to avoid any possibility of interactions between the two
comparators in the same package.
High Speed Design Techniques
The extremely fast speed of the LT1711/LT1712 necessi-
tates careful attention to proper PC board layout and
circuit design in order to prevent oscillations, as with
most high speed comparators. The most common prob-
lem involves power supply bypassing which is necessary
to maintain low supply impedance. Resistance and induc-
tance in supply wires and PC traces can quickly build up
to unacceptable levels, thereby allowing the supply volt-
ages to move as the supply current changes. This move-
ment of the supply voltages will often result in improper
operation. In addition, adjacent devices connected through
an unbypassed supply can interact with each other through
the finite supply impedances.
Bypass capacitors furnish a simple solution to this prob-
lem by providing a local reservoir of energy at the device,
thus keeping supply impedance low. Bypass capacitors
should be as close as possible to the LT1711/LT1712
supply pins. A good high frequency capacitor, such as a
1000pF ceramic, is recommended in parallel with larger
capacitors, such as a 0.1µF ceramic and a 4.7µF tantalum
in parallel. These bypass capacitors should be soldered to
the output ground plane such that the return currents do
not pass through the ground plane under the input cir-
cuitry. The common tie point for these two ground planes
should be at the board ground connection. Such star-
grounding and ground plane separation is extremely im-
portant for the proper operation of ultra high speed circuits.
Poor trace routes and high source impedances are also
common sources of problems. Keep trace lengths as short
as possible and avoid running any output trace adjacent
to an input trace to prevent unnecessary coupling. If
output traces are longer than a few inches, provide proper
termination impedances (typically 100Ω to 400Ω) to
eliminate any reflections that may occur. Also keep source
impedances as low as possible, preferably much less than
1kΩ.
The input and output traces should also be isolated from
one another. Power supply traces can be used to achieve
this isolation as shown in Figure 1, a typical topside layout
of the LT1712 on a multilayer PC board. Shown is the
topside metal etch including traces, pin escape vias and
the land pads for a GN16 LT1712 and its adjacent X7R
0805 bypass capacitors. The V
+
, V
–
and GND traces all
shield the inputs from the outputs. Although the two V
–
pins are connected internally, they should be shorted
together externally as well in order for both to function as
shields. The same is true for the two V
+
pins. The two GND
pins are not connected internally, but in most applications
they are both connected directly to the ground plane.
APPLICATIO S I FOR ATIO
WUUU
171112 F01
Figure 1. Typical LT1712 Topside Metal
for Multilayer PCB Layout
Hysteresis
Another important technique to avoid oscillations is to
provide positive feedback, also known as hysteresis,
from the output to the input. Increased levels of hyster-
esis, however, reduce the sensitivity of the device to input
voltage levels, so the amount of positive feedback should
be tailored to particular system requirements. The
LT1711/LT1712 are completely flexible regarding the
application of hysteresis, due to rail-to-rail inputs and the
complementary outputs. Specifically, feedback resistors
can be connected from one of the outputs to its corre-
sponding input without regard to common mode consid-
erations. Figure 2 shows several configurations.
