1. General description
The HEF4027B-Q100 is an edge-triggered dual JK flip-flop which features independent
set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q
). Data is accepted
when CP is LOW, and transferred to the output on the positive-going edge of the clock.
The active HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are
independent and override the J, K, and CP inputs. The outputs are buffered for best
system performance. Schmitt trigger action makes the clock input highly tolerant of slower
rise and fall times.
It operates over a recommended V
DD
power supply range of 3 V to 15 V referenced to V
SS
(usually ground). Unused inputs must be connected to V
DD
, V
SS
, or another input.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 3) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 3)
Specified from 40 C to +85 C
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-833, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
Complies with JEDEC standard JESD 13-B
3. Applications
Registers
Counters
Control circuits
HEF4027B-Q100
Dual JK flip-flop
Rev. 1 — 26 June 2013 Product data sheet
