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HEF4027BT-Q100J

P1-P3P4-P6P7-P9P10-P12P13-P14
HEF4027B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 26 June 2013 6 of 13
NXP Semiconductors HEF4027B-Q100
Dual JK flip-flop
11. Dynamic characteristics
Table 7. Dynamic characteristics
V
SS
= 0 V; T
amb
= 25
C; for test circuit, see Figure 7; unless otherwise specified.
Symbol Parameter Conditions V
DD
Extrapolation formula
[1]
Min Typ Max Unit
t
PHL
HIGH to LOW
propagation delay
CP Q, Q;
see Figure 4
5 V 78 ns + (0.55 ns/pF)C
L
- 105 210 ns
10 V 29 ns + (0.23 ns/pF)C
L
- 4080ns
15 V 22 ns + (0.16 ns/pF)C
L
- 3060ns
CD Q;
see Figure 4
5 V 93 ns + (0.55 ns/pF)C
L
- 120 240 ns
10 V 33 ns + (0.23 ns/pF)C
L
- 4590ns
15 V 27 ns + (0.16 ns/pF)C
L
- 3570ns
SD Q
;
see Figure 4
5 V 113 ns + (0.55 ns/pF)C
L
- 140 280 ns
10 V 44 ns + (0.23 ns/pF)C
L
-55110ns
15 V 32 ns + (0.16 ns/pF)C
L
- 4080ns
t
PLH
LOW to HIGH
propagation delay
CP Q, Q;
see Figure 4
5 V 58 ns + (0.55 ns/pF)C
L
- 85 170 ns
10 V 27 ns + (0.23 ns/pF)C
L
- 3570ns
15 V 22 ns + (0.16 ns/pF)C
L
- 3060ns
CD Q
;
see Figure 4
5 V 48 ns + (0.55 ns/pF)C
L
- 75 150 ns
10 V 24 ns + (0.23 ns/pF)C
L
- 3570ns
15 V 17 ns + (0.16 ns/pF)C
L
- 2550ns
SD Q;
see Figure 4
5 V 43 ns + (0.55 ns/pF)C
L
- 70 140 ns
10 V 19 ns + (0.23 ns/pF)C
L
- 3060ns
15 V 17 ns + (0.16 ns/pF)C
L
- 2550ns
t
t
transition time see Figure 4 5 V
[2]
10 ns + (1.00 ns/pF)C
L
- 60 120 ns
10 V 9 ns + (0.42 ns/pF)C
L
- 3060ns
15 V 6 ns + (0.28 ns/pF)C
L
- 2040ns
t
su
set-up time J, K CP;
see Figure 5
5 V 5025- ns
10 V 3010- ns
15 V 20 5 - ns
t
h
hold time J, K CP;
see Figure 5
5 V 25 0 - ns
10 V 20 0 - ns
15 V 15 5 - ns
t
W
pulse width CP LOW;
minimum width,
see Figure 5
5 V 8040- ns
10 V 3015- ns
15 V 2412- ns
SD, CD HIGH;
minimum width,
see Figure 6
5 V 9045- ns
10 V 4020- ns
15 V 3015- ns
t
rec
recovery time SD, CD inputs;
see Figure 6
5 V +20 15 - ns
10 V +15 10 - ns
15 V +10 5- ns
HEF4027B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 26 June 2013 7 of 13
NXP Semiconductors HEF4027B-Q100
Dual JK flip-flop
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
[2] t
t
is the same as t
TLH
and t
THL
.
12. Waveforms
f
max
maximum
frequency
CP input;
J = K = HIGH;
see Figure 5
5 V 4 8 - MHz
10 V 12 25 - MHz
15 V 15 30 - MHz
Table 7. Dynamic characteristics
…continued
V
SS
= 0 V; T
amb
= 25
C; for test circuit, see Figure 7; unless otherwise specified.
Symbol Parameter Conditions V
DD
Extrapolation formula
[1]
Min Typ Max Unit
Table 8. Dynamic power dissipation P
D
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter V
DD
Typical formula for P
D
(W) Where:
P
D
dynamic power
dissipation
5 V P
D
= 900 f
i
+ (f
o
C
L
) V
DD
2
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
DD
= supply voltage in V;
(f
o
C
L
) = sum of the outputs.
10 V P
D
= 4500 f
i
+ (f
o
C
L
) V
DD
2
15 V P
D
= 13200 f
i
+ (f
o
C
L
) V
DD
2
V
OH
and V
OL
are typical output voltages levels that occur with the output load.
Measurement points are given in Table 9
.
Fig 4. Waveforms showing rise, fall and transition times and propagation delays
Measurement points are given in Table 9.
Fig 5. Waveforms showing set-up and hold times and minimum clock pulse width
001aae596
CP INPUT
J,K INPUT
t
W
V
M
V
M
1/f
max
t
su
t
h
HEF4027B_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 1 — 26 June 2013 8 of 13
NXP Semiconductors HEF4027B-Q100
Dual JK flip-flop
V
OH
and V
OL
are typical output voltages levels that occur with the output load.
Measurement points are given in Table 9
.
Fig 6. Waveforms showing pulse widths and recovery times
001aae597
SD
INPUT
V
I
0 V
V
I
0 V
V
I
0 V
V
OH
V
OL
CD INPUT
CP INPUT
t
W
t
W
V
M
V
M
V
M
Q OUTPUT
t
rec
t
rec
Table 9. Measurement points
Supply voltage Input Output
V
DD
V
M
V
M
5 V to 15 V 0.5V
DD
0.5V
DD
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
C
L
= load capacitance including jig and probe capacitance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
Fig 7. Test circuit
V
DD
V
I
V
O
001aag182
DUT
C
L
R
T
G
Table 10. Test data
Supply voltage Input Load
V
DD
V
I
t
r
, t
f
C
L
5 V to 15 V V
SS
or V
DD
20 ns 50 pF
P1-P3P4-P6P7-P9P10-P12P13-P14

HEF4027BT-Q100J

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Manufacturer:
Nexperia
Description:
Flip Flops Dual JK flip-flop
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New from this manufacturer.
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