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CY3250-20334QFN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32
September 18, 2006 Document No. 001-05356 Rev. *B 13
CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2. Electrical Specifications
2.3.2 DC General Purpose IO Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, and 2.7V at 25°C and are for design guidance only.
Table 2-5. 5V and 3.3V DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
R
PU
Pull-up Resistor 4 5.6 8 kΩ
V
OH1
High Output Voltage
Port 0, 2, or 3 Pins
Vdd - 0.2 – – V IOH < 10 µA, Vdd > 3.0V, maximum of 10 mA
source current in all IOs.
V
OH2
High Output Voltage
Port 0, 2, or 3 Pins
Vdd - 0.9 – – V IOH = 1 mA, Vdd > 3.0V, maximum of 20 mA
source current in all IOs.
V
OH3
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
Vdd - 0.2 – – V IOH < 10 µA, Vdd > 3.0V, maximum of 10 mA
source current in all IOs.
V
OH4
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
Vdd - 0.9 – – V IOH = 5 mA, Vdd > 3.0V, maximum of 20 mA
source current in all IOs.
V
OH5
High Output Voltage
Port 1 Pins with LDO Regulator Enabled
2.75 3.0 3.2 V IOH < 10 µA, Vdd > 3.1V, maximum of 4 IOs all
sourcing 5 mA.
V
OH6
High Output Voltage
Port 1 Pins with LDO Regulator Enabled
2.2 – – V IOH = 5 mA, Vdd > 3.1V, maximum of 20 mA
source current in all IOs.
V
OL
Low Output Voltage – – 0.75 V IOL = 20 mA, Vdd > 3V, maximum of 60 mA sink
current on even port pins (for example, P0[2]
and P1[4]) and 60 mA sink current on odd port
pins (for example, P0[3] and P1[5]).
V
IL
Input Low Voltage – – 0.8 V Vdd = 3.0 to 5.25.
V
IH
Input High Voltage 2.0 – V Vdd = 3.0 to 5.25.
V
H
Input Hysteresis Voltage – 140 – mV
I
IL
Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 µA.
C
IN
Capacitive Load on Pins as Input 0.5 1.7 5 pF
Package and pin dependent. Temp = 25
o
C.
C
OUT
Capacitive Load on Pins as Output 0.5 1.7 5 pF
Package and pin dependent. Temp = 25
o
C.
Table 2-6. 2.7V DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
R
PU
Pull-up Resistor 4 5.6 8 kΩ
V
OH1
High Output Voltage
Port 0, 2, or 3 Pins
Vdd - 0.2 – – V IOH < 10 µA, maximum of 10 mA source current
in all IOs.
V
OH2
High Output Voltage
Port 0, 2, or 3 Pins
Vdd - 0.5 – – V IOH = 0.2 mA, maximum of 10 mA source cur-
rent in all IOs.
V
OH3
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
Vdd - 0.2 – – V IOH < 10 µA, maximum of 10 mA source current
in all IOs.
V
OH4
High Output Voltage
Port 1 Pins with LDO Regulator Disabled
Vdd - 0.5 – – V IOH = 2 mA, maximum of 10 mA source current
in all IOs.
V
OL
Low Output Voltage – – 0.75 V IOL = 10 mA, maximum of 30 mA sink current
on even port pins (for example, P0[2] and P1[4])
and 30 mA sink current on odd port pins (for
example, P0[3] and P1[5]).
V
IL
Input Low Voltage – – 0.8 V Vdd = 2.4 to 3.0V.
V
IH
Input High Voltage 2.0 – V Vdd = 2.4 to 3.0V.
V
H
Input Hysteresis Voltage – 60 – mV
I
IL
Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 µA.
C
IN
Capacitive Load on Pins as Input 0.5 1.7 5 pF
Package and pin dependent. Temp = 25
o
C.
C
OUT
Capacitive Load on Pins as Output 0.5 1.7 5 pF
Package and pin dependent. Temp = 25
o
C.
September 18, 2006 Document No. 001-05356 Rev. *B 14
CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2. Electrical Specifications
2.3.3 DC Analog Mux Bus Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
2.3.4 DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 2-7. DC Analog Mux Bus Specifications
Symbol Description Min Typ Max Units Notes
R
SW
Switch Resistance to Common Analog Bus – – 400
800
Ω
Ω
Vdd ≥ 2.7V
2.4V ≤ Vdd ≤ 2.7V
Table 2-8. DC POR and LVD Specifications
Symbol Description Min Typ Max Units Notes
V
PPOR0
V
PPOR1
V
PPOR2
Vdd Value for PPOR Trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
2.36
2.60
2.82
2.40
2.65
2.95
V
V
V
Vdd must be greater than or equal to 2.5V
during startup, reset from the XRES pin, or
reset from Watchdog.
V
LVD0
V
LVD1
V
LVD2
V
LVD3
V
LVD4
V
LVD5
V
LVD6
V
LVD7
Vdd Value for LVD Trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.39
2.54
2.75
2.85
2.96
–
–
4.52
2.45
2.71
2.92
3.02
3.13
–
–
4.73
2.51
a
2.78
b
2.99
c
3.09
3.20
–
–
4.83
a. Always greater than 50 mV above V
PPOR
(PORLEV = 00) for falling supply.
b. Always greater than 50 mV above V
PPOR
(PORLEV = 01) for falling supply.
c. Always greater than 50 mV above V
PPOR
(PORLEV = 10) for falling supply.
V
V
V
V
V
V
V
V
September 18, 2006 Document No. 001-05356 Rev. *B 15
CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2. Electrical Specifications
2.3.5 DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Table 2-9. DC Programming Specifications
Symbol Description Min Typ Max Units Notes
Vdd
IWRITE
Supply Voltage for Flash Write Operations 2.70 – – V
I
DDP
Supply Current During Programming or Verify – 5 25 mA
V
ILP
Input Low Voltage During Programming or Verify – – 0.8 V
V
IHP
Input High Voltage During Programming or Verify 2.2 – – V
I
ILP
Input Current when Applying Vilp to P1[0] or P1[1] During
Programming or Verify
– – 0.2 mA Driving internal pull-down resistor.
I
IHP
Input Current when Applying Vihp to P1[0] or P1[1] During
Programming or Verify
– – 1.5 mA Driving internal pull-down resistor.
V
OLV
Output Low Voltage During Programming or Verify – – Vss + 0.75 V
V
OHV
Output High Voltage During Programming or Verify Vdd
- 1.0 – Vdd V
Flash
ENPB
Flash Endurance (per block) 50,000 – – – Erase/write cycles per block.
Flash
ENT
Flash Endurance (total)
a
a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of
25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than
50,000 cycles).
1,800,000 – – – Erase/write cycles.
Flash
DR
Flash Data Retention 10 – – Years
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P32

CY3250-20334QFN

Mfr. #:
Buy CY3250-20334QFN
Manufacturer:
Cypress Semiconductor
Description:
Emulators / Simulators EMULATION KIT PSoC CY8C20334QFN
Lifecycle:
New from this manufacturer.
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