September 18, 2006 Document No. 001-05356 Rev. *B 22
CY8C20234, CY8C20334, CY8C20434 Final Data Sheet 2. Electrical Specifications
2.4.8 AC I
2
C Specifications
The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ T
A
≤ 85°C, 3.0V to 3.6V and -40°C ≤ T
A
≤ 85°C, or 2.4V to 3.0V and -40°C ≤ T
A
≤ 85°C, respectively. Typical parameters
apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.
Figure 2-3. Definition for Timing for Fast/Standard Mode on the I
2
C Bus
Table 2-22. AC Characteristics of the I
2
C SDA and SCL Pins for Vdd ≥ 3.0V
Symbol Description
Standard Mode Fast Mode
Units NotesMin Max Min Max
F
SCLI2C
SCL Clock Frequency 0 100 0 400 kHz
T
HDSTAI2C
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
4.0 –0.6– µs
T
LOWI2C
LOW Period of the SCL Clock 4.7 –1.3– µs
T
HIGHI2C
HIGH Period of the SCL Clock 4.0 –0.6– µs
T
SUSTAI2C
Set-up Time for a Repeated START Condition 4.7 –0.6– µs
T
HDDATI2C
Data Hold Time 0 –0– µs
T
SUDATI2C
Data Set-up Time 250 –
100
a
a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t
SU;DAT
≥ 250 ns must then be met. This will automatically be
the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t
rmax
+ t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
–ns
T
SUSTOI2C
Set-up Time for STOP Condition 4.0 –0.6– µs
T
BUFI2C
Bus Free Time Between a STOP and START Condition 4.7 –1.3– µs
T
SPI2C
Pulse Width of spikes are suppressed by the input fil-
ter.
– – 0 50 ns
Table 2-23. 2.7V AC Characteristics of the I
2
C SDA and SCL Pins (Fast Mode not Supported)
Symbol Description
Standard Mode Fast Mode
Units NotesMin Max Min Max
F
SCLI2C
SCL Clock Frequency 0 100 – – kHz
T
HDSTAI2C
Hold Time (repeated) START Condition. After this
period, the first clock pulse is generated.
4.0 – – – µs
T
LOWI2C
LOW Period of the SCL Clock 4.7 – – – µs
T
HIGHI2C
HIGH Period of the SCL Clock 4.0 – – – µs
T
SUSTAI2C
Set-up Time for a Repeated START Condition 4.7 – – – µs
T
HDDATI2C
Data Hold Time 0 – – – µs
T
SUDATI2C
Data Set-up Time 250 – – –ns
T
SUSTOI2C
Set-up Time for STOP Condition 4.0 – – – µs
T
BUFI2C
Bus Free Time Between a STOP and START Condition 4.7 ––– µs
T
SPI2C
Pulse Width of spikes are suppressed by the input fil-
ter.
– –––ns
SDA
SCL
S
Sr SP
T
BUFI2C
T
SPI2C
T
HDSTAI2C
T
SUSTOI2C
T
SUSTAI2C
T
LOWI2C
T
HIGHI2C
T
HDDATI2C
T
HDSTAI2C
T
SUDATI2C
