September 18, 2006 Document No. 001-05356 Rev. *B 7
1. Pin Information
This chapter describes, lists, and illustrates the CY8C20234, CY8C20334 and CY8C20434 PSoC device pins and pinout configura-
tions.
1.1 Pinouts
The CY8C20x34 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of Digital IO and connection to the common analog bus. However, Vss, Vdd, and XRES are not
capable of Digital IO.
1.1.1 16-Pin Part Pinout
Table 1-1. 16-Pin Part Pinout (QFN**)
Pin
No.
Type
Name Description
CY8C20234 16-Pin PSoC Device
Digital Analog
1 IO I P2[5]
2 IO I P2[1]
3 IOH I P1[7] I2C SCL, SPI SS.
4 IOH I P1[5] I2C SDA, SPI MISO.
5 IOH I P1[3] SPI CLK.
6 IOH I P1[1] CLK*, I2C SCL, SPI MOSI.
7 Power Vss Ground connection.
8 IOH I P1[0] DATA*, I2C SDA.
9 IOH I P1[2]
10 IOH I P1[4] Optional external clock input (EXTCLK).
11 Input XRES Active high external reset with internal
pull down.
12 IO I P0[4]
13 Power Vdd Supply voltage.
14 IO I P0[7]
15 IO I P0[3] Integrating input.
16 IO I P0[1]
CP Power Vss Center pad must be connected to
ground.
LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
** The center pad (CP) on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground,
it should be electrically floated and not connected to any other signal.
QFN
(Top View)
CP
AI, P2[5]
AI, I2C SCL, SPI SS, P1[7]
AI, I2C SDA, SPI MISO, P1[5]
AI, SPI CLK, P1[3]
1
2
3
4
11
10
9
16
15
14
13
P0[3], AI
P0[7], AI
Vdd
P0[4], AI
CLK, I2C SCL, SPI MOSI P1[1]
AI, DATA, I2C SDA, P1[0]
P1[2], AI
AI, P2[1]
P1[4], AI, EXTCLK
XR ES
P0[1], AI
Vss
12
5
6
7
8
