CS5124
http://onsemi.com
6
+
+
+
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+
+
V
CC
UVLO COMP
V
REF
= 5.0 V
OSC
DIS
RAMP
V5
REF
V5
REF
V
REFOK
GND
I
SENSE
V
FB
GATE
V
CC
UVLO
BIAS
SS
S
R
Q
F3
V5
REF
V5
REF
V
CC
LINE AMP
2.0 V
V
V
V
V
V
V
V
V
V
1.91 V/1.83 V
2.62 V/2.45 V
TSHUT
7.7 V/7.275 V
G2
G6
V
÷
490 mV
10 mA
F2
S
R
Q
LINE UVLO COMP
REMOTE
(SLEEP) COMP
150°C/125°C
SS AMP
BLANKING
1000 W
DRIVER
G7
G1
G3
S
R
Q
F1
BLANK
I
COMP
2ND
SET DOMAIN
RESET DOMAIN
170 mV/ms
+
+
+
V
CC
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
+
−
4500 W
1.32 V
2.90 V
SS COMP
Soft−Start LATCH
PWM COMP
V
FB
COMP
60 mV
ENABLE
G5
275 mV
275 mV
1/10
V
2.9 R
R
Figure 2. Block Diagram
THEORY OF OPERATION
Powering the IC
V
CC
can be powered directly from a regulated supply and
requires 500 mA of startup current. The CS5124 includes a
line bias pin (BIAS) that can be used to control a series pass
transistor for operation over a wide input voltage. The BIAS
pin will control the gate voltage of an N−channel MOSFET
placed between V
IN
and V
CC
to regulate V
CC
at 8.0 V.
V
CC
and UVLO Pins
The UVLO pin has three different modes; low power
shutdown, Line UVLO, and normal operation. To illustrate
how the UVLO pin works; assume that V
IN
, as shown in the
application schematic, is ramped up starting at 0 V with the
UVLO pin open. The SS and I
SENSE
pins also start at 0 V.
While the UVLO is below 1.8 V, the IC will remain in a low
current sleep mode and the BIAS pin of the CS5124 is
internally clamped to a maximum of 15 V. When the voltage
on the UVLO pin rises to between 1.8 V and 2.6 V the
reference for the V
CC
UVLO is enabled and V
CC
is
regulated to 8.0 V by the BIAS pin, but the IC remains in a
UVLO state and the output driver does not switch. When the
UVLO pin exceeds 2.6 V and the V
CC
pin exceeds 7.7 V, the
GATE pin is released from a low state and can begin
switching based on the comparison of the I
SENSE
and V
FB
pins. The Soft−Start capacitor begins charging from 0 V at
10 mA. As the capacitor charges, a buffered version of the
capacitor voltage appears on the V
FB
pin and the V
FB
voltage begins to rise. As V
FB
rises the duty cycle increases
until the supply comes into regulation.
Soft−Start
Soft−Start is accomplished by clamping the V
FB
pin 1.32 V
below the SS pin during normal start up and during restart
after a fault condition. When the CS5124 starts, the
Soft−Start capacitor is charged from a 10 mA source from 0
V to 4.9 V. The V
FB
pin follows the Soft−Start pin offset
by −1.32 V until the supply comes into regulation or until
