MUR420 Datasheet MUR420, MUR460, CS5124XDR8G | P7-P9

CS5124

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the Soft−Start error amp is clamped at 2.9 V. During fault

conditions the Soft−Start capacitor is discharged at 10 mA.

Fault Conditions

The CS5124 recognizes the following faults: UVLO off,

Thermal Shutdown, V

REF(OK)

, and Second Current

Threshold. Once a fault is recognized, fault latch F2 is set

and the IC immediately shuts down the output driver and

discharges the Soft−Start capacitor. Soft−Start will begin

only after all faults have been removed and the Soft−Start

capacitor has been discharged to less than 0.275 V. Each

fault will be explained in the following sections.

Under Voltage Lockout (UVLO)

The UVLO pin is tied to typically the midpoint of a

resistive divider between V

and GROUND. During a start

up sequence, this pin must be above 2.6 V in order for the IC

to begin normal operation. If the IC is running and this pin

is pulled below 1.8 V, F2 shuts down the output driver and

discharges the Soft−Start capacitor in order to insure proper

startup. If the UVLO pin is pulled high again before the

Soft−Start capacitor discharges, the IC will complete the

Soft−Start discharge and, if no other faults are present, will

immediately restart the power supply. If the UVLO pin stays

low, then it will enter either the low current sleep mode or the

UVLO state depending on the level of the UVLO pin.

Thermal Shutdown

If the IC junction temperature exceeds approximately

150°C the thermal shutdown circuit sets F2, which shuts

down the output driver and discharges the Soft−Start

capacitor. If no other faults are present the IC will initiate

Soft−Start when the IC junction temperature has been

reduced by 25°C.

REF(OK)

is an internal monitor that insures the internal

regulator is running before any switching occurs. This

function does not trip the fault comparator like the other fault

functions. To insure that Soft−Start will occur at low line

conditions the UVLO divider should be set up so that the

UVLO comparator turns on before the LINE UVLO

comparator.

Second Threshold Comparator

Since the maximum dynamic range of the I

SENSE

signal

in normal operation is 195 mV, any voltage exceeding this

threshold on the I

SENSE

pin is considered a fault and the

PWM cycle is terminated. The 2nd I

COMP

compares the

SENSE

signal with a 275 mV threshold. If the I

SENSE

voltage exceeds the second threshold, F2 is set, the driver

turns off, and the Soft−Start capacitor discharges. After the

Soft−Start capacitor has discharged to less than 0.275 V

Soft−Start will begin. If the fault condition has been

removed the supply will operate normally. If the fault

remains the supply will operate in hiccup mode until the

fault condition is removed.

Comparator

The V

comparator detects when the output voltage is

too high. When the regulated output voltage is too high, the

feedback loop will drive V

low. If V

is less than 0.49 V

the output of the V

comparator will go high and shut the

output driver off.

Oscillator

The internally trimmed, 400 kHz provides the slope

compensation ramp as well as the pulse for enabling the

output driver.

PWM Comparator and Slope Compensation

The CS5124 provides a fixed internal slope compensation

ramp that is subtracted from the feedback signal. The PWM

comparator compares peak primary current to a portion of

the difference of the feedback voltage and slope

compensation ramp. The 170 mV/ms slope compensation

ramp is subtracted from the voltage feedback signal

internally. The difference signal is then divided by ten before

the PWM comparator to provide high noise rejection with a

low voltage across the current sense network. The effective

ramp is 21 mV/ms. A 60 mV nominal offset on the positive

input to the PWM comparator allows for operation with the

SENSE

pin at, or even slightly below GND.

A 4.3 kW pull−up resistor internally connected to a 5.0 V

nominal reference provides the bias current to for an

optocoupler connection to the V

pin.

CS5124

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APPLICATION INFORMATION

UVLO and Thermal Shutdown Interaction

The UVLO pin and thermal shutdown circuit share the

same internal comparator. During high temperature

operation (T

> 100°C) the UVLO pin will interact with the

thermal shutdown circuit. This interaction increases the

turn−on threshold (and hysteresis) of the UVLO circuit. If

the UVLO pin shuts down the IC during high temperature

operation, higher hysteresis (see hysteresis specification)

might be required to enable the IC.

BIAS Pin

The bias pin can be used to control V

as shown in the

main application diagram in Figure 1. In order to provide

adequate phase margin for the bias control loop, the pole

created by the series pass transistor and the V

bypass

capacitor should be kept above 10 kHz. The frequency of

this pole can be calculated by Formula (1).

Pole Frequency +

Transconductance of pass Transistor

2 p C

V(CC)

(1)

The Line BIAS pin shows a significant change in the

regulated V

voltage when sinking large currents. This will

show up as poor line regulation with a low value pull−up

resistor. Typical regulated V

vs BIAS pin sink current is

shown in Figure 3.

Figure 3. Regulated V

vs. BIAS Sink Current

5.0 mΑ 10 mΑ 20 mΑ 50 mΑ 100 mΑ 200 mΑ

Bias Current (I

BIAS

)

7.9

8.0

8.1

8.2

8.3

The BIAS pin and associated components form a high

impedance node. Care should be taken during PCB layout to

avoid connections that could couple noise into this node. To

ensure adequate design margin between the regulated V

and the Low V

Lockout voltage, a guaranteed minimum

differential between the two values is specified (see

electrical characteristcs).

Gate Drive

Rail to rail gate driver operation can be obtained (up to

13.5 V) over a range of MOSFET input capacitance if the

gate resistor value is kept low. Figure 5 shows the high gate

drive level vs. the series gate resistance with V

= 8.0 V

driving an IRF220.

Figure 4. Gate Drive vs. Gate Resistor Driving an

IRF220 (V

= 8.0 V)

Gate Resistor Value

Peak Voltage

8.5

0.3 0.5 2.5 5.0

8.0

7.5

7.0

6.5

6.0

A large negative dv/dt on the power MOSFET drain will

couple current into the gate driver through the gate to drain

capacitance. If this current is kept within absolute maximum

ratings for the GATE pin it will not damage the IC. However

if a high negative dv/dt coincides with the start of a PWM

duty cycle, there will be small variations in oscillator

frequency due to current in the controller substrate. If

required, this can be avoided by choosing the transformer

ratio and reset circuit so that a high dv/dt does not coincide

with the start of a PWM cycle, or by clamping the negative

voltage on the GATE pin with a Schottky diode

First Current Sense Threshold

During normal operation the peak primary current is

controlled by the level of the V

pin (as determined by the

control loop) and the current sense network. Once the signal

on the I

SENSE

pin exceeds the level determined by V

the PWM cycle terminates. During high output currents the

pin will rise until it reaches the V

clamp. The first

current sense threshold determines the maximum signal

allowed on the I

SENSE

pin before the PWM cycle is

terminated. Under this condition the maximum peak current

is determined by the V

Clamp, the slope compensation

ramp, the PWM comparator offset voltage and the PWM on

time. The nominal first current threshold varies with on time

and can be calculated from Formulas (2) and (3) below.

1st Threshold +

2.9 V * 170 mVńms T

* 60 mV

(2)

When the output current is high enough for the I

SENSE

to exceed the first threshold, the PWM cycle terminates

early and the converter begins to function more like a current

source. The current sense network must be chosen so that the

peak current during normal operation does not exceed the

first current sense threshold.

Second Current Sense Threshold

The second threshold is intended to protect the converter

from overheating by switching to a low duty cycle mode

when there are abnormally high fast rise currents in the

CS5124

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converter. If the second current sense threshold is tripped,

the converter will shut off and restart in Soft−Start mode

until the high current condition is removed. The dead time

after a second threshold overcurrent condition will primarily

be determined by the time required to charge the Soft−Start

cap from 0.275 V nominal to 1.32 V.

The second threshold will only be reached when a high

dv/dt is present at the current sense pin. The signal must be

fast enough to reach the second threshold before the first

threshold turns off the driver. This will normally happen if

the forward inductor saturates or when there is a shorted

load.

Excessive filtering of the current sense signal, a low value

current sense resistor, or even an inductor that does not

saturate during heavy output currents can prevent the second

threshold from being reached. In this case the first current

sense threshold will trip during each cycle of high output

current conditions. The first threshold will limit output

current but some components, especially the output rectifier,

can overheat due to higher than normal average output

current.

Slope Compensation

Current mode converters operating at duty cycles in

excess of 50% require an artificial ramp to be added to the

current waveform or subtracted from the feedback

waveform. For the current loop to be stable the artificial

ramp must be equivalent to at least 50% of the inductor

current down slope and is typically chosen between 75% to

100% of the inductor down current down slope.

To choose an inductor value such that the internal slope

compensation ramp will be equal to a certain fraction of the

inductor down current slope use the Formula (4).

Internal Ramp

OUT

) V

RECTIFIER

)

SECONDARY

PRIMARY

SENSE

Slo

e Value Factor + Inductor Value

(

)

(4)

Calculating the nominal inductor value for an artificial

ramp equivalent to 100% of the current inductor down slope

at CS5124 nominal conditions, a 5.0 V output, a 200 mW

current sense resistor and a 4:1 transformer ratio yields

20 mV

(5.0 V ) 0.3 V)

0.2 W 1.0 + 13.2 mH

(5)

To check that the slope compensation ramp will be greater

than 50% of the inductor down under all conditions,

substitute the minimum internal slope compensation value

and use 0.5 for the slope compensation value. Then check

that the actual inductor value will always be greater than the

inductor value calculated.

Powering the CS5124 from a Transformer Winding

There are numerous ways to power the CS5124 from a

transformer winding to enable the converter to be operated

at high efficiency over a wide input range.

The CS5124 application circuit in Figure 1 is a flyback

converter that uses a second flyback winding to power V

R4 improves V

regulation with load changes by snubbing

the turn off spike. Once the turn off spike has subsided the

voltage of this winding is voltage proportional to the voltage

on the main flyback winding. This voltage is regulated

because the main winding is clamped by the regulated output

voltage.

A flyback winding from a forward transformer can also be

used to power V

. Ideally the transformer volt−second

product of a forward converter would be constant over the

range of line voltages and load currents; and the transformer

inductance could be chosen to store the required level of

energy during each cycle to power V

. Even though the

flyback energy is not directly regulated it would remain

constant. Unfortunately in a real converter there are many

nonideal effects that degrade regulation. Transformer

inductance varies, converter frequency varies, energy stored

in primary leakage inductance varies with output current,

stray transformer capacitances and various parasitics all

effect the level of energy available for V

. If too little

energy is provided to V

, the bootstrapping circuit must

provide power and efficiency will be reduced. If too much

energy is provided V

rises and may damage the controller.

If this approach is taken the circuit must be carefully

designed and component values must be controlled for good

regulation.

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