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5PB11xx MARCH 28, 2017 21 ©2017 Integrated Device Technology, Inc.
Revision History
Rev. Date Originator Description of Change
A 03/20/15 B. Chandhoke Initial release.
B 05/19/15 B. Chandhoke 1. Expanded Output Enable function text in General Description, and within the note
under “Output Logic Table”.
2. Updated all “Buffer Additive Phase Jitter, RMS” conditions from 125MHz to 156.25MHz.
C 06/09/15 B. Chandhoke 1. Corrected typos in part numbers in DC Electrical Tables.
2. Updated existing Output Rise/Fall Time specs for 5pF load.
3. Added additional Output Rise/Fall specs for 2pF load.
D 06/15/15 B. Chandhoke Fixed typos in Output Rise/Fall Time 5pF specs for CL conditions; should be 5pF; not 2pF.
E 06/22/15 B. Chandhoke Changed 3.3V Operating Voltage spec from 3.15V min to 3.135V min; 3.45V max to
3.465V max.
F 08/24/15 B. Chandhoke 1. Added 5PB1104CMGI
W orderable part.
2. Updated Abs Max Ratings table for “Output Enable and All outputs” and “CLKIN”;
changed -0.5 V to -0.4 and added -0.4 to... respectively.
G 05/13/16 H.G. Replace NDG20 package outline drawing with latest version.
H 12/15/16 J. Chen Updated marking diagrams for all TSSOP devices.
J 02/10/17 Y.G. Change Propagation Delay maximum spec in 1.8V AC electrical characterization table
from 2.2 to 2.5ns.
K 03/28/17 Y.G. 1. Updated Propagation Delay specifications for 5PB1106/08/10; 2.5V and 3.3V.
2. Updated output-output skew maximum specifications for 5PB1106; 1.8V, 2.5V, 3.3V.
3. Updated legal disclaimer.
4. Updated package outline drawings.
