FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 2 Rev A 06/10/15
844003-01 DATA SHEET
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Number Name Type Description
1,
24
DIV_SELB0,
DIV_SELB1
Input Pullup
Division select pin for Bank B. Default = HIGH.
LVCMOS/LVTTL interface levels. See Table 3B.
2 VCO_SEL Input Pullup
VCO select pin. When Low, the PLL is bypassed and the crystal reference or
REF_CLK (depending on XTAL_SEL setting) are passed directly to the output
dividers. Has an internal pullup resistor so the PLL is not bypassed by default.
LVCMOS/LVTTL interface levels.
3 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled. Has an
internal pulldown resistor so the power-up default state of outputs and dividers
are enabled. LVCMOS/LVTTL interface levels.
4V
DDO_A
Power Output supply pin for Bank A outputs.
5, 6 QA0, nQA0 Output Differential output pair. LVDS interface levels.
7 OEB Input Pullup
Output enable Bank B. Active High outputs are enable. When logic HIGH, the
output pairs on Bank B are enabled. When logic LOW, the output pairs are in a
high impedance state. Has an internal pullup resistor so the default power-up
state of outputs are enabled. LVCMOS/LVTTL interface levels. See Table 3E.
8 OEA Input Pullup
Output enable Bank A. Active High output enable. When logic HIGH, the output
pair in Bank A is enabled. When logic LOW, the output pair is in a high
impedance state. Has an internal pullup resistor so the default power-up state of
output is enabled. LVCMOS/LVTTL interface levels. See Table 3D.
9 FB_DIV Input Pulldown
Feedback divide select. When Low (default), the feedback divider is set for ÷25.
When HIGH, the feedback divider is set for ÷32. See Table 3C.
LVCMOS/LVTTL interface levels.
10 V
DDA
Power Analog supply pin.
11 V
DD
Power Core supply pin.
12,
13
DIV_SELA0,
DIV_SELA1
Input Pullup
Division select pin for Bank A. Default = HIGH. See Table 3A.
LVCMOS/LVTTL interface levels.
14 GND Power Power supply ground.
15,
16
XTAL_OUT,
XTAL_IN
Input
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit
with a single-ended reference clock.
17 REF_CLK Input Pulldown
Single-ended reference clock input. Has an internal pulldown resistor to pull to
low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
18 XTAL_SEL Input Pullup
Crystal select pin. Selects between the single-ended REF_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected by
default. LVCMOS/LVTTL interface levels.
19, 20 nQB1, QB1 Output Differential output pair. LVDS interface levels.
21, 22 nQB0, QB0 Output Differential output pair. LVDS interface levels.
23 V
DDO_B
Power Output supply pin for Bank B outputs.
