FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 13 Rev A 06/10/15
844003-01 DATA SHEET
Recommendations for Unused Input and Output Pins
Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
REF_CLK Input
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1k resistor can be tied from the REF_CLK to ground.
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
Outputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated
with 100 across. If they are left floating, we recommend that there
is no trace attached.
3.3V LVDS Driver Termination
A general LVDS interface is shown in Figure 4 In a 100 differential
transmission line environment, LVDS drivers require a matched load
termination of 100 across near the receiver input. For a multiple
LVDS outputs buffer, if only partial outputs are used, it is
recommended to terminate the unused outputs.
Figure 4. Typical LVDS Driver Termination
3.3V
LVDS Driver
R1
100Ω
+
3.3V
50Ω
50Ω
100Ω Differential Transmission Line
Rev A 06/10/15 14 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
844003-01 DATA SHEET
EPAD Thermal Release Path
In order to maximize both the removal of heat from the package and
the electrical performance, a land pattern must be incorporated on
the Printed Circuit Board (PCB) within the footprint of the package
corresponding to the exposed metal pad or exposed heat slug on the
package, as shown in Figure 5. The solderable area on the PCB, as
defined by the solder mask, should be at least the same size/shape
as the exposed pad/slug area on the package to maximize the
thermal/electrical performance. Sufficient clearance should be
designed on the PCB between the outer edges of the land pattern
and the inner edges of pad pattern for the leads to avoid any shorts.
While the land pattern on the PCB provides a means of heat transfer
and electrical grounding from the package to the board through a
solder joint, thermal vias are necessary to effectively conduct from
the surface of the PCB to the ground plane(s). The land pattern must
be connected to ground through these vias. The vias act as “heat
pipes”. The number of vias (i.e. “heat pipes”) are application specific
and dependent upon the package power dissipation as well as
electrical conductivity requirements. Thus, thermal and electrical
analysis and/or testing are recommended to determine the minimum
number needed. Maximum thermal and electrical performance is
achieved when an array of vias is incorporated in the land pattern. It
is recommended to use as many vias connected to ground as
possible. It is also recommended that the via diameter should be 12
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
desirable to avoid any solder wicking inside the via during the
soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
to eliminate any solder voids between the exposed heat slug and the
land pattern. Note: These recommendations are to be used as a
guideline only. For further information, refer to the Application Note
on the Surface Mount Assembly of Amkor’s Thermally/Electrically
Enhance Leadfame Base Package, Amkor Technology.
Figure 5. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)
GROUND PLANE
LAND PATTERN
SOLDER
THERMAL VIA
EXPOSED HEAT SLUG
(GROUND PAD)
PIN
PIN PAD
SOLDER
PIN
PIN PAD
SOLDER
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 15 Rev A 06/10/15
844003-01 DATA SHEET
Power Considerations
This section provides information on power dissipation and junction temperature for the 844003-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 844003-01 is the sum of the core power plus the analog power plus the power dissipated in the load(s). The
following is the power dissipation for V
DD
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
DD_MAX
* (I
DD_MAX
+ I
DDA_MAX
) = 3.465V * (135mA + 12mA) = 509.36mW
Power (outputs)
MAX
= V
DDO_MAX
* I
DDO_MAX
= 3.465V * 80mA = 277.20mW
Total Power
_MAX
= 509.36mW + 277.20mW = 786.56mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The
maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 32.1°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.787W * 32.1°C/W = 95.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board.
Table 7. Thermal Resistance
JA
for 24 Lead TSSOP, E-Pad, Forced Convection
JA
by Velocity
Meters per Second 012
Multi-Layer PCB, JEDEC Standard Test Boards 32.1°C/W 35.5°C/W 26.9°C/W

844003BG-01LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CRYSTAL TO LVDS FREQ SYNT
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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