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844003BG-01LFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Rev A 06/10/15 10 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
844003-01 DATA SHEET
Parameter Measurement Information
3.3V LVDS Output Load AC Test Circuit
Output Skew
Output Duty Cycle/Pulse Width/Period
RMS Phase Jitter
Bank Skew
Output Rise/Fall Time
GND
V
DD,
V
DDA,
V
DDO_A,
V
DDO_B
Qx
nQx
Qy
nQy
nQA0,
nQB0, nQB1
QA0,
QB0, QB1
Phase Noise Mas
k
Offset Frequency
f
1
f
2
Phase Noise Plot
RMS Jitter = Area Under the Masked Phase Noise Plot
Noise Power
nQB0
QB0
nQB1
QB1
tsk(b)
20%
80%
80%
20%
t
R
t
F
V
OD
nQA0,
nQB0, nQB1
QA0,
QB0, QB1
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER 11 Rev A 06/10/15
844003-01 DATA SHEET
Parameter Measurement Information, continued
Offset Voltage Setup Differential Output Voltage Setup
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform- ance,
power supply isolation is required. The 844003-01 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V
DD,
V
DDA,
V
DDO_A
and V
DDO_B
should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic V
DD
pin and also shows that V
DDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the V
DDA
pin.
Figure 1. Power Supply Filtering
V
DD
V
DDA
3.3V
10Ω
10µF.01µF
.01µF
Rev A 06/10/15 12 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
844003-01 DATA SHEET
Crystal Input Interface
The 844003-01 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 19.53125MHz or 25MHz, 18pF parallel resonant
crystal and were chosen to minimize the ppm error.
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS signals, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50 applications, R1 and R2
can be 100. This can also be accomplished by removing R1 and
making R2 50.
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
22pF
C2
22pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

844003BG-01LFT

Mfr. #:
Buy 844003BG-01LFT
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner CRYSTAL TO LVDS FREQ SYNT
Lifecycle:
New from this manufacturer.
Delivery:
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