December 1990 2
Philips Semiconductors Product specification
Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173
FEATURES
• Gated input enable for hold (do nothing) mode
• Gated output enable control
• Edge-triggered D-type register
• Asynchronous master reset
• Output capability: bus driver
• I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT173 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT173 are 4-bit parallel load registers with
clock enable control, 3-state buffered outputs (Q
0
to Q
3
)
and master reset (MR).
When the two data enable inputs (E
1
and E
2
) are LOW, the
data on the D
n
inputs is loaded into the register
synchronously with the LOW-to-HIGH clock (CP)
transition. When one or both E
n
inputs are HIGH one
set-up time prior to the LOW-to-HIGH clock transition, the
register will retain the previous data. Data inputs and clock
enable inputs are fully edge-triggered and must be stable
only one set-up time prior to the LOW-to-HIGH clock
transition.
The master reset input (MR) is an active HIGH
asynchronous input. When MR is HIGH, all four flip-flops
are reset (cleared) independently of any other input
condition.
The 3-state output buffers are controlled by a 2-input NOR
gate. When both output enable inputs (OE
1
and OE
2
) are
LOW, the data in the register is presented to the Q
n
outputs. When one or both OE
n
inputs are HIGH, the
outputs are forced to a high impedance OFF-state. The
3-state output buffers are completely independent of the
register operation; the OE
n
transition does not affect the
clock and reset operations.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; t
r
=t
f
=6ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in µW):
P
D
=C
PD
× V
CC
2
× f
i
+∑ (C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑ (C
L
× V
CC
2
× f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay
CP to Q
n
MR to Q
n
C
L
= 15 pF; V
CC
=5V
17
13
17
17
ns
ns
f
max
maximum clock frequency 88 88 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation
capacitance per flip-flop
notes 1 and 2 20 20 pF
