December 1990 10
Philips Semiconductors Product specification
Quad D-type flip-flop; positive-edge trigger;
3-state
74HC/HCT173
AC WAVEFORMS
Fig.6 Waveforms showing the clock (CP) to
output (Q
n
) propagation delays, the clock
pulse width, the output transition times and
the maximum clock pulse frequency.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.7 Waveforms showing the master reset (MR)
pulse width, the master reset to output (Q
n
)
propagation delays and the master reset to
clock (CP) removal time.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.8 Waveforms showing the 3-state enable and
disable times.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.9 Waveforms showing the data set-up and hold
times from input (En, D
n
) to clock (CP).
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
