NB3N51034DTR2G Datasheet NB3N51034DTG, NB3N51034DTR2G | P1-P3

June, 2014 − Rev. 2

1 Publication Order Number:

NB3N51034/D

NB3N51034

3.3V, Crystal to 100MHz/

200MHz Quad HCSL/LVDS

Clock Generator

The NB3N51034 is a high precision, low phase noise clock generator

that supports spread spectrum designed for PCI Express applications.

This device takes a 25 MHz fundamental mode parallel resonant crystal

and generates 4 differential HCSL/LVDS outputs at 100 MHz or

200 MHz (See Figure 8 for LVDS interface). The NB3N51034 provides

selectable spread options of −0.5%, −1.0%, −1.5%, for applications

demanding low Electromagnetic Interference (EMI) as well as

optimum performance with no spread option.

Features

• Uses 25 MHz Fundamental Mode Parallel Resonant Crystal

• Power Down Mode

• 4 Low Skew HCSL or LVDS Outputs

• OE Tri−States Outputs

• Spread of −0.5%, −1.0%, −1.5% and No Spread

• PCIe Gen 1, Gen 2, Gen 3 Compliant

• Phase Noise (SS OFF) @ 100 MHz:

Offset Noise Power

100 Hz −110 dBc/Hz

1 kHz −123 dBc/Hz

10 kHz −134 dBc/Hz

100 kHz −137 dBc/Hz

1 MHz −138 dBc/Hz

10 MHz −154 dBc/Hz

• Operating Supply Voltage Range 3.3 V ±5%

• Industrial Temperature Range −40°C to +85°C

• Functionally Compatible with IDT557−05,

IDT5V41066, IDT5V41236 with enhanced performance

• These are Pb−Free Devices

Applications

• Networking

• Consumer

• Computing and Peripherals

• Industrial Equipment

• PCIe Clock Generation Gen 1, Gen 2 and Gen 3

End Products

• Switch and Router

• Set Top Box, LCD TV

• Servers, Desktop Computers

• Automated Test Equipment

Figure 1. NB3N51034 Simplified Logic Diagram

Phase

Detector

Charge

Pump

Clock Buffer

Crystal Oscillator

CLK2

X1/CLK

VCO

25 MHz Clock

or Crystal

GND

S0 S1 OE

IREF

HCSL

Output

CLK3

HCSL

Output

CLK0

HCSL

Output

CLK1

HCSL

Output

S2 PD

Spread Spectrum

Circuit

= VDDODA = VDDXD

GND = GNDODA = GNDXD

MARKING

DIAGRAM

TSSOP−20

DT SUFFIX

CASE 948E

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

ORDERING INFORMATION

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G = Pb−Free Package

(Note: Microdot may be in either location)

NB3N

1034

ALYWG

NB3N51034

http://onsemi.com

VDDXD

X1/CLK

CLK0

CLK1

GNDODA

CLK0

Figure 2. Pin Configuration (Top View)

VDDODA

912GNDXD

10 11IREF

CLK1

CLK2

CLK3

CLK2

CLK3

Table 1. PIN DESCRIPTION

Pin Symbol I/O Description

1 VDDXD Power Connect to a +3.3 V source.

2 S0 Input LVTTL/LVCMOS frequency select input 0. Internal pullup resistor to VDDXD. See output select

table 2 for details.

3 S1 Input LVTTL/LVCMOS frequency select input 1. Internal pullup resistor to VDDXD. See output select

Table 2 for details.

4 S2 Input LVTTL/LVCMOS frequency select input 2. Internal pullup resistor to VDDXD. See output select

Table 2 for details.

5 X1/CLK Input Crystal interface or single−ended reference clock input.

6 X2 Output Crystal interface. Float this pin for reference clock input CLK.

7 PD Input LVTTL/LVCMOS power down input. Assert this pin LOW to enter power down mode. Internal

pull−up resistor to VDDXD.

8 OE Input Output enable. Tri−state output (High=enable outputs, Low=disable outputs). Internal pull−up

resistor.

9 GNDXD Power Connect to digital circuit ground.

10 IREF Output Precision resistor attached to this pin is connected to the internal current reference.

11 CLK3 HCSL or

LVDS Output

Inverted clock output. (For LVDS levels see Figure 8)

12 CLK3 HCSL or

LVDS Output

Noninverted clock output. (For LVDS levels see Figure 8)

13 CLK2 HCSL or

LVDS Output

Inverted clock output. (For LVDS levels see Figure 8)

14 CLK2 HCSL or

LVDS Output

Noninverted clock output. (For LVDS levels see Figure 8)

15 VDDODA Power Connect to a +3.3 V analog source.

16 GNDODA Power Output and analog circuit ground.

17 CLK1 HCSL or

LVDS Output

Inverted clock output. (For LVDS levels see Figure 8)

18 CLK1 HCSL or

LVDS Output

Noninverted clock output. (For LVDS levels see Figure 8)

19 CLK0 HCSL or

LVDS Output

Inverted clock output. (For LVDS levels see Figure 8)

20 CLK0 HCSL or

LVDS Output

Noninverted clock output. (For LVDS levels see Figure 8)

NB3N51034

http://onsemi.com

Table 2. OUTPUT FREQUENCY AND SPREAD

SPECTRUM SELECT TABLE

S2* S1* S0* Spread%

Spread

Type

Output

Frequency

0 0 0 −0.5 Down 100

0 0 1 −1.0 Down 100

0 1 0 −1.5 Down 100

0 1 1 No Spread N/A 100

1 0 0 −0.5 Down 200

1 0 1 −1.0 Down 200

1 1 0 −1.5 Down 200

1 1 1 No Spread N/A 200

*Pins S2, S1 and S0 default high when left open.

Recommended Crystal Parameters

Crystal Fundamental AT−Cut

Frequency 25 MHz

Load Capacitance 16−20 pF

Shunt Capacitance, C0 7 pF Max

Equivalent Series Resistance 50 W Max

Initial Accuracy at 25 °C ±20 ppm

Temperature Stability ±30 ppm

Aging ±20 ppm

Table 3. ATTRIBUTES

Characteristic Value

Internal Input Default State Resistor (OE, Sx, PD)

110 kW

ESD Protection Human Body Model 2 kV

Moisture Sensitivity, Indefinite Time Out of Dray Pack (Note 1) Level 1

Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in

Transistor Count 132,000

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

1. For additional information, see Application Note AND8003/D.

P1-P3 P4-P6 P7-P9 P10-P11

NB3N51034DTR2G

Mfr. #:

Buy NB3N51034DTR2G

Manufacturer:

ON Semiconductor

Description:

Clock Generators & Support Products 3.3V Crystal to 100/ 200MHz Qd HCSL/LVDS

Lifecycle:

New from this manufacturer.

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NB3N51034DTR2G

NB3N51034DTR2G

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