NB3N51034DTR2G

NB3N51034
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7
PHASE NOISE
Figure 3. Typical Phase Noise Plot at 100 MHz; (f
CLKIN
= 25 MHz Crystal , f
CLKOUT
= 100 MHz SS OFF,
RMS Phase Jitter for Integration Range 12 kHz to 20 MHz = 414 fs, Output Termination = HCSL type)
Figure 4. Typical Phase Noise Plot at 200 MHz; (f
CLKIN
= 25 MHz Crystal , f
CLKOUT
= 200 MHz SS OFF,
RMS Phase Jitter for Integration Range 12 kHz to 20 MHz = 406 fs, Output Termination = HCSL type)
OFFSET FREQUENCY (Hz)
OFFSET FREQUENCY (Hz)
NOISE POWEER (dBc/Hz)NOISE POWEER (dBc/Hz)
NB3N51034
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8
APPLICATION INFORMATION
Crystal Input Interface
Figure 5 shows the NB3N51034 device crystal oscillator
interface using a typical parallel resonant crystal. The device
crystal connections should include pads for small capacitors
from X1 to ground and from X2 to ground. These capacitors,
C
1
and C
2
, need to consider the stray capacitances of the
board and are used to match the nominally required crystal
load capacitance C
L
. A parallel crystal with loading
capacitance C
L
= 18 pF would use C
1
= 26 pF and C
2
= 26 pF
as nominal values, assuming approximately 2 pF of stray
capacitance per trace and approximately 8 pF of internal
capacitance.
C
L
= (C
1
+ C
stray
+ C
in
) / 2; C
1
= C
2
The frequency accuracy and duty cycle skew can be
fine-tuned by adjusting the C
1
and C
2
values. For example,
increasing the C
1
and C
2
values will reduce the operational
frequency.
Figure 5. Crystal Interface Loading
C
1
= 26 pF
C
2
= 26 pF
X1
X2
Fundamental Mode
Parallel Resonant Crystal
18 pF Load
Power Supply Filter
In order to isolate the NB3N51034 from system power
supply, noise decoupling is required. The 10 mF and a 0.1 mF
cap from supply pins to GND decoupling capacitor has to be
connected between V
DD
(pins 1 and 15) and GND (pins 9
and 6). It is recommended to place decoupling capacitors as
close as possible to the device to minimize lead inductance.
Termination
The output buffer structure is shown in the Figure 6.
Figure 6. Simplified Output Structure
R
REF
CLKx CLKxIREF
2.6 mA
475 W
HCSL / LVDS
termination
14 mA
NB3N51034
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9
The outputs can be terminated to drive HCSL receiver
(see Figure 7) or LVDS receiver (see Figure 8). HCSL output
interface requires 49.9 W termination resistors to GND for
generating the output levels. LVDS output interface may not
require the 100 W near the LVDS receiver if the receiver has
internal 100 W termination. An optional series resistor R
L
may be connected to reduce the overshoots in case of
impedance mismatch.
HCSL INTERFACE
Figure 7. Typical Termination for HCSL Output Driver and Device Evaluation
Z
o
= 50 W
Z
o
= 50 W
R
L
= 50 W R
L
= 50 W
R
L
* = 33.2 W
R
L
* = 33.2 W
NB3N51034 Receiver
CLK0
CLK0
Z
o
= 50 W
Z
o
= 50 W
R
L
= 50 W R
L
= 50 W
R
L
* = 33.2 W
R
L
* = 33.2 W
CLK3
CLK3
*Optional
R
REF
= 475 W
IREF
LVDS COMPATIBLE INTERFACE
Figure 8. Typical Termination for LVDS Device Load
Z
o
= 50 W
Z
o
= 50 W
R
L
= 150 W
R
L
= 150 W
NB3N51034 Receiver
CLK0
CLK0
Z
o
= 50 W
Z
o
= 50 W
R
L
= 150 W
R
L
= 150 W
CLK3
CLK3
100 W
100 W
100 W**
100 W**
LVDS Device Load
R
REF
= 475 W
IREF
R
L
* = 33.2 W
R
L
* = 33.2 W
R
L
* = 33.2 W
R
L
* = 33.2 W
*Optional
**Not required if LVDS receiver
has 100 Ohm internal termination

NB3N51034DTR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Clock Generators & Support Products 3.3V Crystal to 100/ 200MHz Qd HCSL/LVDS
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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