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ADF4108BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
ADF4108 Data Sheet
Rev. E | Page 12 of 20
REFERENCE COUNTER LATCH MAP
LDP
0
1
ABP2 ABP1
0 0 2.9ns
0 1 1.3ns TEST MODE ONLY. DO NOT USE
1 0 6.0ns
1 1 2.9ns
R14
R13 R12 .......... R3 R2 R1
0
0 0 .......... 0 0 1 1
0 0 0 .......... 0 1 0 2
0 0 0 .......... 0 1 1 3
0 0 0 .......... 1 0 0 4
. .
. .......... . . . .
. . . ..........
. . . .
. . . .......... . . .
.
1 1 1 .......... 1 0 0
16380
1 1 1 .......... 1 0 1 16381
1 1 1 .......... 1 1 0 16382
1 1
1 .......... 1 1 1 16383
X
= DON’T CARE
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11
DB10
DB9 DB8 DB7 DB6
DB5 DB4 DB3 DB2 DB1 DB0
C2 (0)
C1 (0)R1R2R3R4R5R6R7R8R9R10R11R12R13R14ABP1
ABP2
T1T2LDP
DB21DB22DB23
0 0
X
RESERVED
LOCK
DETECT
PRECISION
TEST
MODE BITS
ANTI-
BACKLASH
WIDTH
14-BIT REFERENCE COUNTER
CONTROL
BITS
DIVIDE RATIO
ANTIBACKLASH PULSE WIDTH
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION.
OPERATION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION.
06015-022
Figure 16. Reference Counter Latch Map
Data Sheet ADF4108
Rev. E | Page 13 of 20
AB COUNTER LATCH MAP
DB20
DB19
DB18 DB17
DB16 DB15 DB14
DB13 DB12 DB11
DB10 DB9
DB8 DB7
DB6
DB5
DB4 DB3
DB2 DB1
DB0
C2 (0) C1 (1)A1A2A3A4A5B1B2B3B4B5B6B7B8B9B10B11B12B13 A6
DB21
DB22DB23
G1
0 0
0
1
1
0
F4 (FUNCTION LATCH)
FASTLOCK ENABLE
1 1
A6 A5 .......... A2 A1
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 60
1 1 .......... 0 1 61
1 1 .......... 1 0 62
1 1 .......... 1 1 63
X X
B13 B12 B11 B3 B2 B1
0 0 0 .......... 0 0 0
0 0 0 .......... 0 0 1
0 0 0 .......... 0 1 0
0 0 0 .......... 0 1 1
3
. . . .......... . . .
.
. . . .......... . . .
.
. . . .......... . . .
.
1 1 1 .......... 1 0 0
8188
1 1 1 .......... 1 0 1
8189
1 1 1 .......... 1 1 0
8190
1 1 1 .......... 1 1 1
8191
X = DON’T CARE
RESERVED
13-BIT B COUNTER
6-BIT A COUNTER
CONTROL
BITS
CP GAIN
A COUNTER
DIVIDE RATIO
B COUNTER DIVIDE RATIO
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
THESE BITS ARE NOT USED
BY THE DEVICE AND ARE
DON'T CARE BITS.
OPERATION
G1
CP GAIN
CHARGE PUMP CURRENT
SETTING 1 IS PERMANENTLY USED.
CHARGE PUMP CURRENT
SETTING 2 IS PERMANENTLY USED.
CHARGE PUMP CURRENT
SETTING 1 IS USED.
CHARGE PUMP CURRENT IS
SWITCHED TO SETTING 2. THE
TIME SPENT IN SETTING 2 IS
DEPENDENT ON WHICH FASTLOCK
MODE IS USED. SEE FUNCTION
LATCH DESCRIPTION.
N = BP + A, P IS PRESCALER VALUE SET IN THE FUNCTION
LATCH. B MUST BE GREATER THAN OR EQUAL TO A. FOR
CONTINUOUSLY ADJACENT VALUES OF (N × F
REF
), AT THE
OUTPUT, N
MIN
IS (P
2
– P).
06015-023
Figure 17. AB Counter Latch Map
ADF4108 Data Sheet
Rev. E | Page 14 of 20
FUNCTION LATCH MAP
P2 P1
0 0 8/9
0 1 16/17
1 0 32/33
1 1 64/65
PD2 PD1 MODE
0
X
X
1
X 0
1 0 1
1 1 1
CPI6 CPI5 CPI4
CPI3 CPI2 CPI1
3kΩ 5.1kΩ 11kΩ
0 0 0 1.06 0.625 0.289
0 0 1 2.12 1.25 0.580
0 1 0 3.18 1.875 0.870
0 1 1 4.24 2.5 1.160
1 0 0 5.30 3.125 1.450
1 0 1 6.36 3.75 1.730
1 1 0 7.42 4.375 2.020
1 1 1 8.50 5.0 2.320
TC4 TC3 TC2 TC1
0 0 0 0 3
0 0 0 1 7
0 0 1 0 11
0 0 1 1 15
0 1 0 0 19
0 1 0 1 23
0 1 1 0 27
0 1 1 1 31
1 0 0 0 35
1 0 0 1 39
1 0 1 0 43
1 0 1 1 47
1 1 0 0 51
1 1 0 1 55
1 1 1 0 59
1 1 1 1 63
F4
0
1
1
M3 M2 M1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
F3
0
1
F2
0
1
F1
0
1
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11
DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C2 (1) C1 (0)
F1
PD1
M1
M2M3F3P1P2 CPI1CPI2CPI5
CPI6
TC4PD2 F2
CPI3CPI4
DB21
TC3 TC2 TC1
DB22DB23
F4
F5
F5
X
0
1
NEGATIVE
POSITIVE
PRESCALER
VALUE
POWER-
DOWN 2
CURRENT
SETTING
2
CURRENT
SETTING
1
TIMER COUNTER
CONTROL
FASTLOCK
MODE
FASTLOCK
ENABLE
CP THREE-
STATE
MUXOUT
CONTROL
POWER-
DOWN 1
COUNTER
RESET
CONTROL
BITS
PHASE DETECTOR
POLARITY
COUNTER
OPERATION
NORMAL
R, A, B COUNTERS
HELD IN RESET
CHARGE PUMP
OUTPUT
NORMAL
THREE-STATE
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
FASTLOCK MODE
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
DV
DD
R DIVIDER OUTPUT
N-CHANNEL OPEN-DRAIN
LOCK DETECT
SERIAL DATA OUTPUT
DGND
OUTPUT
TIMEOUT
(PFD CYCLES)
I
CP
(mA)
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
CE PIN
PRESCALER VALUE
PD
POLARITY
06015-024
Figure 18. Function Latch Map
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

ADF4108BCPZ

Mfr. #:
Buy ADF4108BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Freq Synthesizer
Lifecycle:
New from this manufacturer.
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