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ADF4108BCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Data Sheet ADF4108
Rev. E | Page 3 of 20
SPECIFICATIONS
AV
DD
= DV
DD
= 3.3 V ± 2%, AV
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 kΩ, dBm referred to 50 Ω, T
A
= T
MIN
to
T
MAX
, unless otherwise noted.
Table 1.
Parameter B Version
1
B Chips
2
(Typ)
Unit Test Conditions/Comments
RF CHARACTERISTICS See Figure 11 for input circuit
RF Input Frequency (RF
IN
) 1.0/8.0 1.0/8.0 GHz min/max For lower frequencies, ensure slew rate (SR) > 320 V/µs
RF Input Sensitivity −5/+5 −5/+5 dBm min/max
Maximum Allowable Prescaler
Output Frequency
3
300 300 MHz max P = 8
325 325 MHz max P = 16
REF
IN
CHARACTERISTICS
REF
IN
Input Frequency 20/250 20/250 MHz min/max For f < 20 MHz, ensure SR > 50 V/µs
REF
IN
Input Sensitivity
4
0.8/V
DD
0.8/V
DD
V p-p min/max Biased at AV
DD
/2
5
REF
IN
Input Capacitance 10 10 pF max
REF
IN
Input Current ±100 ±100 µA max
PHASE DETECTOR
Phase Detector Frequency
6
104 104 MHz max
CHARGE PUMP Programmable; see Figure 18
I
CP
Sink/Source
High Value 5 5 mA typ With R
SET
= 5.1 kΩ
Low Value 625 625 µA typ
Absolute Accuracy 2.5 2.5 % typ With R
SET
= 5.1 kΩ
R
SET
Range 3.0/11 3.0/11 kΩ typ See Figure 18
I
CP
Three-State Leakage 1 1 nA typ 1 nA typical; T
A
= 25°C
Sink and Source Current Matching 2 2 % typ 0.5 V ≤ V
CP
≤ V
P
− 0.5 V
I
CP
vs. V
CP
1.5 1.5 % typ 0.5 V ≤ V
CP
≤ V
P
− 0.5 V
I
CP
vs. Temperature 2 2 % typ V
CP
= V
P
/2
LOGIC INPUTS
V
IH
, Input High Voltage 1.4 1.4 V min
V
IL
, Input Low Voltage 0.6 0.6 V max
I
INH
, I
INL
, Input Current
±1
µA max
C
IN
, Input Capacitance 10 10 pF max
LOGIC OUTPUTS
V
OH
, Output High Voltage 1.4 1.4 V min Open-drain output chosen; 1 kΩ pull-up resistor to 1.8 V
V
OH
, Output High Voltage V
DD
− 0.4 V
DD
− 0.4 V min CMOS output chosen
I
OH
, Output High Current 100 100 µA max
V
OL
, Output Low Voltage 0.4 0.4 V max I
OL
= 500 µA
POWER SUPPLIES
AV
DD
3.2/3.6 3.2/3.6 V min/max
DV
DD
AV
DD
AV
DD
V
P
AV
DD
/5.5 AV
DD
/5.5 V min/max AV
DD
≤ V
P
≤ 5.5 V
I
DD
(AI
DD
+ DI
DD
)
7
17
mA max
15 mA typ
I
P
0.4 0.4 mA max T
A
= 25°C
Power-Down Mode (AI
DD
+ DI
DD
)
8
10 10 µA typ
ADF4108 Data Sheet
Rev. E | Page 4 of 20
Parameter B Version
1
B Chips
2
(Typ) Unit Test Conditions/Comments
NOISE CHARACTERISTICS
Normalized Phase Noise Floor
(PN
SYNTH
)
9
−223 −223 dBc/Hz typ PLL loop B/W = 500 kHz, measured at 100 kHz offset
Normalized 1/f Noise (PN
1_f
)
10
−122 −122 dBc/Hz typ 10 kHz offset; normalized to 1 GHz
Phase Noise Performance
11
@ VCO output
7900 MHz Output
12
−81 −81 dBc/Hz typ @ 1 kHz offset and 1 MHz PFD frequency
Spurious Signals
7900 MHz Output
12
−82
dBc typ
@ 1 MHz offset and 1 MHz PFD frequency
1
Operating temperature range (B version) is −40°C to +85°C.
2
The B chip specifications are given as typical values.
3
This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that
is less than this value.
4
AV
DD
= DV
DD
= 3.3 V.
5
AC coupling ensures AV
DD
/2 bias.
6
Guaranteed by design. Sample tested to ensure compliance.
7
T
A
= 25°C; AV
DD
= DV
DD
= 3.3 V; P = 32; RF
IN
= 8 GHz, f
PFD
= 200 kHz, REF
IN
= 10 MHz.
8
T
A
= 25°C; AV
DD
= DV
DD
= 3.3 V; R = 16,383; A = 63; B = 891; P = 32; RF
IN
= 7.0 GHz.
9
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log F
PFD
. PN
SYNTH
= PN
TOT
− 10 log F
PFD
− 20 log N.
10
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, f
RF
,
and at a frequency offset, f, is given by PN = PN
1_f
+ 10 log(10 kHz/f) + 20 log(f
RF
/1 GHz). All phase noise measurements were performed with the EV-ADF4108EBZ1 and
the Agilent E5500 phase noise system. Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
11
The phase noise is measured with the EV-ADF4108EB1Z evaluation board, with the ZComm CRO8000Z VCO. The spectrum analyzer provides the REF
IN
for the
synthesizer (f
REFOUT
= 10 MHz @ 0 dBm).
12
f
REFIN
= 10 MHz; f
PFD
= 1 MHz; f
RF
= 7900 MHz; N = 7900; loop B/W = 30 kHz, VCO = ZComm CRO8000Z.
Data Sheet ADF4108
Rev. E | Page 5 of 20
TIMING CHARACTERISTICS
AV
DD
= DV
DD
= 3.3 V ± 2%, AV
DD
≤ V
P
≤ 5.5 V, AGND = DGND = CPGND = 0 V, R
SET
= 5.1 kΩ, dBm referred to 50 Ω, T
A
= T
MIN
to
T
MAX
, unless otherwise noted.
Table 2.
Parameter
1
Limit
2
(B Version) Unit Test Conditions/Comments
t
1
10 ns min DATA to CLOCK setup time
t
2
10 ns min DATA to CLOCK hold time
t
3
25 ns min CLOCK high duration
t
4
25 ns min CLOCK low duration
t
5
10 ns min CLOCK to LE setup time
t
6
20 ns min LE pulse width
1
Guaranteed by design but not production tested.
2
Operating temperature range (B Version) is −40°C to +85°C.
CLOCK
DB22
DB2
DATA
LE
t
1
LE
DB23 (MSB)
t
2
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t
3
t
4
t
6
t
5
06015-002
Figure 2. Timing Diagram
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

ADF4108BCPZ

Mfr. #:
Buy ADF4108BCPZ
Manufacturer:
Analog Devices Inc.
Description:
Phase Locked Loops - PLL Freq Synthesizer
Lifecycle:
New from this manufacturer.
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