MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
10 ______________________________________________________________________________________
Detailed Description
Internal Linear Regulator (VL)
An internal regulator produces the 5V supply (VL) that
powers the PWM controller, MOSFET driver, logic, ref-
erence, and other blocks within the IC. This 5V low-
dropout (LDO) linear regulator supplies up to 35mA for
MOSFET gate-drive and external loads. For supply volt-
ages between 4.5V and 5.5V, connect VL to V+. This
bypasses the VL regulator, which improves efficiency,
and allows the IC to function at lower input voltages.
On-Time One-Shot and
Switching Frequency
The heart of the PWM is the one-shot that sets the high-
side switch on time. This fast, low-jitter, adjustable one-
shot includes circuitry that varies the on time in response
to both input and output voltages. The high-side switch
on time is inversely proportional to the input voltage as
measured by the EN/HSD input, and is directly propor-
tional to the VTT output voltage. This algorithm results in
a nearly constant switching frequency despite the lack
of a fixed-frequency clock generator. The switching fre-
quency can be selected to avoid noise-sensitive regions
such as the 455kHz IF band. Also, with a constant
switching frequency, the inductor ripple-current operat-
ing point remains relatively constant, resulting in easy
design methodology and predictable output voltage rip-
ple. The general formula for on time (t
ON
) is:
where V
HSD
and V
DDR
are the voltages measured at
EN/HSD and DDR, respectively, and K = 1.7µs. The
value of N depends on the configuration of FSEL and is
listed in Table 1.
The actual switching frequency, which is given by the
following equation, varies slightly due to voltage drop
across the on-resistance of the MOSFETs and the DC
resistance of the output inductor:
where I
O
is the output current, R
DSONH
is the on-resis-
tance of the high-side MOSFET, R
DSONL
is the on-
resistance of the low-side MOSFET, and R
DC
is the DC
resistance of the output inductor. The above equation is
valid only when FSEL is connected to ground. The ideal
switching frequency for V
DDR
= 2.5V is about 550kHz.
The switching frequency, which is almost constant,
results in relatively constant inductor ripple current
regardless of input voltage and predictable output volt-
age ripple. This feature eases design methodology.
Switching frequency increases for positive (sourcing)
load current and decreases for negative (sinking) load
current, due to the changing voltage drop across the
low-side MOSFET, which changes the inductor-current
discharge ramp rate. The on times guaranteed in the
Electrical Characteristics tables are also influenced by
switching delays caused by the loading effect of the
external power MOSFETs.
VTTR Reference
The MAX1917 VTTR output is capable of sourcing or
sinking up to 25mA of current. The V
TTR
output voltage
is one half of the voltage applied to the DDR input.
Bypass VTTR with at least a 1.0µF capacitor.
EN/HSD Function
In order to reduce pin count and package size, the
MAX1917 features a dual-function input pin, EN/HSD.
When EN/HSD is connected to ground, the internal cir-
cuitry powers off, reducing current consumption to less
than 5µA typical (circuit of Figure 6). To enable normal
operation, connect EN/HSD to the drain of the high-side
MOSFET. If EN/HSD is not grounded, it becomes an
input that monitors the high-side MOSFET drain voltage
(converter input voltage) and uses that measurement to
calculate the appropriate on time for the converter.
Therefore, EN/HSD must be connected to this node in
order for the controller to operate properly.
f
VIR R
tVIR R
kHz
S
DDR O DSONL DC
ON IN O DSONL DSONH
=
×+ +
()
×+
()
()
×
05
10
3
.
tKN
V
V
s
ON
HSD
DDR
× ×
1
2
µ
FSEL CONNECTED
TO
N t
ON
(µs) FREQUENCY (kHz) CONDITION
Ground 1.00 0.91 550 0.5V
DDR
/ V
HSD
= 0.5
REF 1.33 1.25 400 0.5V
DDR
/ V
HSD
= 0.5
Floating 2.00 1.66 300 0.5V
DDR
/ V
HSD
= 0.5
VL 3.00 2.50 200 0.5V
DDR
/ V
HSD
= 0.5
Table 1. Configuration of FSEL
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
______________________________________________________________________________________ 11
Voltage Reference
The voltage at REF is nominally 2.00V. Connect a 0.22µF
ceramic bypass capacitor between REF and GND.
Overcurrent Protection
The current-limit circuit employs a unique valley cur-
rent-sensing algorithm that uses the on-state resistance
of the low-side MOSFET as a current-sensing element.
If the current-sense signal is greater than the current-
limit threshold, the PWM is not allowed to initiate a new
cycle. The actual peak current is greater than the cur-
rent-limit threshold by an amount equal to the inductor
ripple current. Therefore, the exact current-limit charac-
teristic and maximum load capability are a function of
the MOSFET on-resistance, inductor value, and input
voltage. The reward for this uncertainty is robust, loss-
less overcurrent sensing. There is also a negative cur-
rent limit that prevents excessive reverse inductor
currents when V
OUT
is sinking current. The negative
current-limit threshold is set to approximately 110% of
the positive current limit, and tracks the positive current
limit when ILIM is adjusted. The current-limit threshold
can be adjusted with an external resistor (R
ILIM
) at ILIM.
A precision 5µA pullup current source at ILIM sets a
voltage drop on this resistor, adjusting the current-limit
threshold from <50mV to >200mV. In the adjustable
mode, the current-limit threshold voltage is precisely
1/10th the voltage seen at ILIM.
Therefore, choose R
ILIM
equal to 2k/mV of the cur-
rent-limit threshold. The threshold defaults to 100mV
when ILIM is connected to VL. The logic threshold for
switchover to the 100mV default value is approximately
V
L
- 1V. The adjustable current limit can accommodate
various MOSFETs. A capacitor in parallel with R
ILIM
can
provide a variable soft-start function.
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signals seen by LX and PGND. The IC must
be mounted close to the low-side MOSFET with short,
direct traces making a Kelvin-sense connection to the
source and drain terminals. See the PC Board Layout
section.
Voltage Positioning
The quick-PWM control architecture responds virtually
instantaneously to transient load changes and elimi-
nates the control loop delay of conventional PWM con-
trollers. As a result, a large portion of the voltage
deviation during a step load change is from the equiva-
lent series resistance (ESR) of the output capacitors.
For DDR termination applications, the maximum
allowed voltage deviation is ±40mV for any output load
transition from sourcing current to sinking current.
Passive voltage positioning adjusts the converters out-
put voltage based on its load current to optimize tran-
sient response and minimize the required output
capacitance. Voltage positioning is implemented by
connecting a 2m resistor as shown in Figure 1.
MOSFET Drivers
The DH and DL drivers are optimized for driving mod-
erate-size, high-side and larger, low-side power
MOSFETs and are optimized for 2.5V and 5V input volt-
ages. The drivers are sized to drive MOSFETs that can
deliver up to 25A output current. An adaptive dead-
time circuit monitors the DL output and prevents the
POK
V+
DDR
EN/HSD
REF
GND
ILIM
VTT
VTTR
PGND
VL
BST
DH
LX
DL
FSEL
R
BST
MAX1917
Figure 2. Increasing the On Time of the High-Side MOSFET
POK
V+
DDR
EN/HSD
REF
GND
ILIM
VTT
VTTR
PGND
VL
BST
DH
LX
DL
FSEL
4 x 270µF
2V
V
OUT
V
IN
VTTR
R
DRP
2m
MAX1917
Figure 1. Using a Resistor for Voltage Positioning
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
12 ______________________________________________________________________________________
high-side FET from turning on until DL is fully off. There
must be a low-resistance, low-inductance path from the
DL driver to the MOSFET gate in order for the adaptive
dead-time circuit to work properly. Otherwise, the
sense circuitry in the MAX1917 interprets the MOSFET
gate as off while there is actually still charge left on the
gate. Use very short, wide traces measuring 10
squares to 20 squares (50mils to 100mils wide if the
MOSFET is 1in from the MAX1917). The dead time at
the other edge (DH turning off) is determined by a fixed
35ns (typ) internal delay. The internal pulldown transis-
tor that drives DL low is robust, with a 0.5 (typ) on-
resistance. This helps prevent DL from being pulled up
during the fast rise time of the inductor node, due to
capacitive coupling from the drain to the gate of the
massive low-side synchronous-rectifier MOSFET. Some
combinations of high- and low-side FETs may be
encountered that cause excessive gate-drain coupling,
which can lead to efficiency-killing, EMI-producing
shoot-through currents. This can often be remedied by
adding a resistor (R
BST
) in series with BST, which
increases the turn-on time of the high-side FET without
degrading the turn-off time (Figure 2).
POK
V+
DDR
EN/HSD
REF
GND
ILIM
VTT
VTTR
PGND
VL
BST
DH
LX
DL
FSEL
2.5V
C2
2 x 330µF
6V
C1
1µF
6.3V
C8
0.47µF/10V
V+
V
DDR
PGND
C3
4.7µF
10V
C4
0.47µF
10V
C7
1µF/6.3V
C9
0.47µF/25V
2.5V
5.5V TO 14V
1.25V AT 7A
L1
0.68µH/9A
Q2
IRF7463
Q1
IRF7463
D1
CMPSH-3
Q3
2N7002K
R3
20k
R2
5.1k
VL
VL
SHDN
POK
VL
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS.
C6
6 x 270µF
2V
C5
2 x 10µF
6.3V
V
OUT
V
IN
VTTR
MAX1917
3
10
2
1
7
5
6
8
11
14
15
16
12
13
4
9
Figure 3. Typical Application Circuit for 1.25V at 7A Output
Typical Application Circuits

MAX1917EEE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Controllers Track/Sink/Source Synchronous Buck
Lifecycle:
New from this manufacturer.
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