MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
______________________________________________________________________________________ 13
POK
V+
DDR
EN/HSD
REF
GND
ILIM
VTT
VTTR
PGND
VL
BST
DH
LX
DL
FSEL
2.5V
C2
2 x 330µF
6V
C1
1µF
6.3V
C8
0.47µF/10V
V+
V
DDR
PGND
C3
4.7µF
10V
C4
0.47µF
10V
C7
1µF/6.3V
C9
0.47µF/25V
2.5V
5.5V TO 14V
1.25V AT 7A
L1
0.68µH/9A
Q2
IRF7463
Q1
IRF7463
D1
CMPSH-3
Q3
2N7002K
R3
20k
R2
5.1k
VL
VL
SHDN
POK
VL
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS
C6
4 x 270µF
2V
V
OUT
V
IN
VTTR
MAX1917
2m
3
10
2
1
7
5
6
8
11
14
15
16
12
13
4
9
Typical Application Circuits (continued)
POK
V+
DDR
EN/HSD
REF
GND
ILIM
VTT
VTTR
PGND
VL
BST
DH
LX
DL
FSEL
2.5V
C2
330µF
6V
C1
1µF
6.3V
C8
0.47µF/10V
V+
V
DDR
PGND
C3
2.2µF
10V
C4
0.22µF
10V
C7
1µF/6.3V
C9
0.47µF/25V
2.5V
5.5V TO 14V
1.25V AT 3.5A
L1
1.0µH/5A
Q2
IRF7811W
Q1
IRF7811W
D1
CMPSH-3
Q3
2N7002K
R3
20k
R2
5.1k
VL
VL
SHDN
POK
VL
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS.
C6
3 x 270µF
2V
C5
10µF
6.3V
V
OUT
V
IN
VTTR
MAX1917
3
10
2
1
7
5
6
8
11
14
15
16
12
13
4
9
Figure 5. Typical Application Circuit for 1.25V at 3.5A Output
Figure 4. Typical Application Circuit for 1.25V at 7A Output Using Voltage Positioning
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
14 ______________________________________________________________________________________
POK
V+
DDR
EN/HSD
REF
GND
ILIM
VTT
VTTR
PGND
VL
BST
DH
LX
DL
FSEL
4.5V TO 15V
C2
4 x 330µF
6V
C1
1µF
25V
C8
0.47µF/10V
PGND
C3
4.7µF
10V
C4
0.47µF
10V
C9
0.22µF
25V
2.5V
2.5V AT 12A
L1
0.75µH/24A
Q2
IRF7822
Q1
IRF7822
D1
CMPSH-3
Q3
2N7002K
R3
20k
R2
5.1k
R4
15k
0.1%
R5
10k
0.1%
5V
POK
VL
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS
C6
3 x 560µF
4V
C5
1µF
6.3V
V
OUT
V
IN
R6
MAX1917
SHDN
3
10
2
1
7
5
6
8
11
14
15
16
12
13
4
9
Figure 7. Circuit to Generate a Fixed 2.5V at 12A Output with a Wide Input Voltage Range
POK
V+
DDR
EN/HSD
REF
GND
ILIM
VTT
VTTR
PGND
VL
BST
DH
LX
DL
FSEL
2.5V
C2
330µF
6V
C1
1µF
6.3V
C8
0.47µF/10V
V+
V
DDR
PGND
C3
2.2µF
10V
C4
0.22µF
10V
C7
1µF/10V
C9
0.47µF/25V
2.5V
5.5V TO 14V
1.25V AT 3.5A
L1
1.0µH/5A
Q2
IRF7811W
Q1
IRF7811W
D1
CMPSH-3
Q3
Si1029X
R3
20k`
R2
10k
VL
VL
SHDN
POK
VL
OUTPUT CAPACITORS ARE SELECTED TO COMPLY WITH JEDEC SPECIFICATIONS.
C6
3 x 270µF
2V
C5
10µF
6.3V
V
OUT
V
IN
VTTR
MAX1917
3
10
2
1
7
5
6
8
11
14
15
16
12
13
4
9
Figure 6. Typical Application Circuit Using P/N-Channel MOSFETs for EN to Minimize the Supply Current from V
IN
in Shutdown Mode
Typical Application Circuits (continued)
MAX1917
Tracking, Sinking and Sourcing, Synchronous Buck
Controller for DDR Memory and Termination Supplies
______________________________________________________________________________________ 15
Design Procedure
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple current ratio). The
primary design trade-off is in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
1) Input Voltage Range. The maximum value
(V
IN(MAX)
) must accommodate the worst-case high
input voltage. The minimum value (V
IN(MIN)
) must
account for the lowest input voltage after drops due
to connectors, fuses, and battery selector switches.
If there is a choice at all, lower input voltages result
in better efficiency.
2) Maximum Load Current. There are two values to
consider. The peak load current (I
LOAD(MAX)
)
determines the instantaneous component stresses
and filtering requirements, and thus drives output
capacitor selection, inductor saturation rating, and
the design of the current-limit circuit. The continu-
ous load current (I
LOAD
) determines the thermal
stresses and thus drives the selection of input
capacitors, MOSFETs, and other critical heat-con-
tributing components.
3) Switching Frequency. This determines the basic
trade-off between size and efficiency. The optimal
frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are
proportional to frequency and V
IN
2
. The optimum
frequency is also a moving target, due to rapid
improvements in MOSFET technology that are mak-
ing higher frequencies more practical.
4) Inductor Operating Point. This provides trade-offs
between size and efficiency. Low inductor values
cause large ripple currents, resulting in the smallest
size but poor efficiency and high output noise. The
minimum practical inductor value is one that causes
the circuit to operate at the edge of critical conduc-
tion (where the inductor current just touches zero
with every cycle at maximum load). Inductor values
lower than this grant no further size-reduction benefit.
The inductor ripple current also impacts transient-
response performance, especially at low V
IN
- V
OUT
dif-
ferentials. Low inductor values allow the inductor
current to slew faster, replenishing charge removed
from the output filter capacitors by a sudden load step.
The amount of output sag is also a function of the maxi-
mum duty factor, which can be calculated from the on
time and minimum off time:
Output Inductor Selection
The switching frequency (on time) and operating point
(% ripple or LIR) determine the inductor value as follows:
Example: I
LOAD(MAX)
= 7A, V
OUT
= 1.25V, f = 550kHz,
50% ripple current or LIR = 0.5:
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered
iron is inexpensive and can work well at 200kHz. The
core must be large enough not to saturate at the peak
inductor current:
(I
PEAK
): I
PEAK
= I
LOAD(MAX)
+ (LIR / 2) (I
LOAD(MAX)
)
Output Capacitor Selection
The output filter capacitor must have low enough ESR
to meet output ripple and load-transient requirements,
yet have high enough ESR to satisfy stability require-
ments. Also, the capacitance value must be high
enough to absorb the inductor energy going from a
positive full-load to negative full-load condition or vice
versa without incurring significant over/undershoot. In
DDR termination applications where the output is sub-
ject to violent load transients, the output capacitors
size depends on how much ESR is needed to prevent
the output from dipping too low under a load transient.
Ignoring the sag due to finite capacitance:
In DDR applications, V
DIP
= 40mV, the output capaci-
tors size depends on how much ESR is needed to
maintain an acceptable level of output voltage ripple:
R
V
LIR I
mV
A
m
ESR
PP
LOAD MAX
×
=
×
=Ω
()
.
.
9
05 7
257
R
V
I
mV
A
m
ESR
DIP
LOAD MAX
≤==
()
.
40
14
285
L
V
kHz A
HH=
××
µ
()
125
550 0 5 7
065 068
.
.
..
L
V
f LIR I
OUT
LOAD MAX
=
××
()
V
IL
C DUTY V V
kHz
SAG
LOAD MAX
f IN MIN OUT
=
()
×
×× ×
()
()
()
2
2

MAX1917EEE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Controllers Track/Sink/Source Synchronous Buck
Lifecycle:
New from this manufacturer.
Delivery:
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