MAX1917EEE+ Datasheet MAX1917EEE+, MAX1917EEE+T | P16-P18

MAX1917

Tracking, Sinking and Sourcing, Synchronous Buck

Controller for DDR Memory and Termination Supplies

16 ______________________________________________________________________________________

The actual microfarad capacitance value required

relates to the physical size needed to achieve low ESR,

as well as to the chemistry of the capacitor technology.

As a result, the capacitor is usually selected by ESR

and voltage rating rather than by capacitance value

(this is true of tantalums, OS-CONs, POSCAPs, and

other electrolytics).

Input Capacitor Selection

The input capacitor must meet the ripple current

requirement (I

RMS

) imposed by the switching currents.

Nontantalum chemistries (ceramic, aluminum, or OS-

CON) are preferred due to their superior surge current

capacity:

Setting the Current Limit

The minimum current-limit threshold must be great

enough to support the maximum load current when the

current limit is at the minimum tolerance value. The val-

ley of the inductor current occurs at I

LOAD(MAX)

minus

half of the ripple current. For example:

LIMIT(LOW)

> I

LOAD(MAX)

- (LIR / 2) ✕ I

LOAD(MAX)

where I

LIMIT(LOW)

= minimum current-limit threshold

voltage divided by the R

DS(ON)

of Q2. For the

MAX1917, the minimum current-limit threshold (100mV

default setting) is 50mV. Use the worst-case maximum

value for R

DS(ON)

from the MOSFET Q2 data sheet, and

add some margin for the rise in R

DS(ON)

with tempera-

ture. A good general rule is to allow 0.5% additional

resistance for each °C of temperature rise.

When adjusting the current limit, use a 1% tolerance

ILIM

resistor to prevent a significant increase of errors

in the current-limit tolerance.

Setting the Voltage Positioning

The droop resistor, R

DRP

, in series with the output

inductor before the output capacitor, sets the droop

voltage, V

DRP

. Choose R

DRP

such that the output volt-

age at the maximum load current, including ripple, is

just above the lower limit of the output tolerance:

DRP

introduces some power dissipation, which is

given by:

PD(DRP) = R

DRP

✕ I

OUT(MAX)

DRP

should be chosen to handle this power dissipation.

MOSFET Power Dissipation

Worst-case conduction losses occur at the duty-factor

extremes. For the high-side MOSFET, the worst-case

power dissipation due to resistance occurs at minimum

input voltage:

PD(Q1) = (V

OUT

/ V

IN(MIN)

) ✕ (I

LOAD

) ✕ (R

DS(ON)

)

Generally, a small high-side MOSFET is desired in order

to reduce switching losses at high input voltages.

However, the R

DS(ON)

required to stay within package

power-dissipation limits often limits how small the

MOSFET can be. Again, the optimum occurs when the

switching (AC) losses equal the conduction (R

DS(ON)

)

losses. Calculating the power dissipation in Q1 due to

switching losses is challenging because it must allow for

difficult-to-quantify factors that influence the turn-on and

turn-off times. These factors include the internal gate

resistance, gate charge, threshold voltage, source

inductance, and PC board layout characteristics. The fol-

lowing switching loss calculation provides only a very

rough estimate and is no substitute for breadboard eval-

uation, preferably including a check using a thermocou-

ple mounted on Q1:

where C

RSS

is the reverse transfer capacitance of Q1

and I

GATE

is the peak gate-drive source/sink current.

For the low-side MOSFET, Q2, the worst-case power

dissipation always occurs at maximum input voltage:

PD(Q2) = (1 - V

OUT

/ V

IN(MAX)

) ✕ I

LOAD

✕ R

DS(ON)

PD SWITCHING

CV fI

RSS IN MAX LOAD

GATE

()

×××

VVV

DRP

OUT TYP OUT MIN RIPPLE

OUT MAX

−−

() ()

()

VVV

RMS LOAD

OUT IN OUT

=×

×−

()













MAX1917

Tracking, Sinking and Sourcing, Synchronous Buck

Controller for DDR Memory and Termination Supplies

______________________________________________________________________________________ 17

The absolute worst case for MOSFET power dissipation

occurs under heavy overloads that are greater than or

equal to I

LOAD(MAX)

. To protect against this condition,

design the circuit to tolerate:

LOAD

= I

LIMIT(HIGH)

+ (LIR / 2) (I

LOAD

(MAX))

where I

LIMIT(HIGH)

is the maximum valley current

allowed by the current-limit circuit, including threshold

tolerance and on-resistance variation. If short-circuit

protection without overload protection is enough, a nor-

mal I

LOAD

value can be used for calculating compo-

nent stresses.

Control IC Power Dissipation

MAX1917 has on-chip MOSFETs drivers (DH and DL)

that dissipate the power loss due to driving the external

MOSFETs. Power dissipation due to a MOSFET driver is

given by:

where Q

and Q

are the total gate charge of the

high-side and low-side MOSFETs, respectively. Select

the switching frequency and V+ correctly to ensure the

power dissipation does not exceed the package power

dissipation requirement.

Applications Information

PC Board Layout

Careful PC board layout is critical to achieving low

switching losses and clean, stable operation. The

switching power stage requires particular attention. If

possible, mount all of the power components on the top

side of the board with their ground terminals flush

against one another. Follow these guidelines for good

PC board layout:

1) Keep the high-current paths short, especially at the

ground terminals. This practice is essential for sta-

ble, jitter-free operation.

2) Connect GND and PGND together as close to the

IC as possible.

3) Keep the power traces and load connections short.

This practice is essential for high efficiency. The

use of thick copper PC boards (2oz vs. 1oz) can

enhance full-load efficiency by 1% or more.

Correctly routing PC board traces is a difficult task

that must be approached in terms of fractions of

centimeters, where a single mΩ of excess trace

resistance causes a measurable efficiency penalty.

4) LX and PGND connections to Q2 for current limiting

must be made using Kelvin-sense connections in

order to guarantee the current-limit accuracy. With

8-pin SO MOSFETs, this is best done by routing

power to the MOSFETs from outside using the top

copper layer, while tying in PGND and LX inside

(underneath) the 8-pin SO package.

5) When trade-offs in trace lengths must be made, it is

preferable to allow the inductor charging path to be

made longer than the discharge path. For example,

it is better to allow some extra distance between the

input capacitors and the high-side MOSFET than to

allow distance between the inductor and the low-

side MOSFET or between the inductor and the out-

put filter capacitor.

6) Ensure that the VTT feedback connection to C

OUT

is short and direct. In some cases, it may be desir-

able to deliberately introduce some trace length

(droop resistance) between the FB inductor node

and the output filter capacitor.

7) VTT feedback sense point should also be as close

as possible to the load connection.

8) Route high-speed switching nodes away from sen-

sitive analog nodes (DDR, EN/HSD, REF, ILIM).

9) Make all pin-strap control input connections (ILIM,

etc.) to GND or VL close to the chip, and do not

connect to PGND.

Chip Information

TRANSISTOR COUNT: 2708

PROCESS: BiCMOS

PVfQQ I

DR S GH GL VTTR

()

×× +

()

MAX1917

Tracking, Sinking and Sourcing, Synchronous Buck

Controller for DDR Memory and Termination Supplies

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

QSOP.EPS

Package Information

(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,

go to www.maxim-ic.com/packages.)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MAX1917EEE+

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