NCP81252
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13
Remote Voltage Sense
A high performance differential amplifier is provided to
accurately sense the output voltage of the regulator. The
VSP and VSN inputs should be connected to the regulators
output voltage sense points. The output (DIFOUT) of the
remote sense amplifier is a sum of the error voltage (between
the output VSP−VSN and the DAC), a load−line voltage
VDROOP, and a 1.3 V DC bias.
V
DIFOUT
+
ǒ
V
VSP
* V
VSN
Ǔ
)
ǒ
1.3 V * V
DAC
Ǔ
) V_DROOP
(eq. 1)
The VDROOP voltage is a half of the voltage difference
between the CSCOMP pin and the CSREF pin.
V
DROOP
+ 0.5 @ V
CS
+ 0.5 @
ǒ
V
CSREF
* V
CSCOMP
Ǔ
(eq. 2)
The DIFOUT signal then goes through a compensation
network and into the inverting input (FB pin) of an error
amplifier. The non−inverting input of the error amplifier is
connected to the same 1.3 V used for the differential sense
amplifier output bias.
Current
Sense
CSCOMP
CSREF
CSSUM
38
39
40
L
DCR
Ccs1
Rcs2
Rcs3
SW
VOUT
Vcs
Rcs1
Ccs2
Rcs_NTC
I
OUT
0.5
V
DROOP
ILIM
37
R
ILIM
ICCMAX
&
IOUT
&
ILIM
IOUT
36
R
IOUT
ICCMAX
35
R
ICCMAX
Figure 7. Differential Current−Sense Circuit Diagram
Differential Current Sense
The differential current−sense circuit diagram is shown in
Figure 7. An internally−used voltage signal Vcs,
representing the inductor current level, is the voltage
difference between CSREF and CSCOMP. The output side
of the inductor is used to create a low impedance virtual
ground. The current−sense amplifier actively filters and
gains up the voltage applied across the inductor to recover
the voltage drop across the inductors DC resistance (DCR).
RCS_NTC is placed close to the inductor to sense the
temperature. This allows the filter time constant and gain to
be a function of the Rth_NTC resistor and compensate for
the change in the DCR with temperature. The DC gain in the
current sensing loop is
G
CS
+
V
CS
V
DCR
+
V
CSREF
* V
CSCOMP
I
OUT
@ DCR
+
R
CS
R
CS3
(eq. 3)
Where
R
CS
+ R
CS2
)
R
CS1
@ R
CS_NTC
R
CS1
) R
CS_NTC
(eq. 4)
The values of Rcs1 and Rcs2 are set based on a 220k NTC
thermistor and the temperature effect of the inductor and
thus usually they should not need to be changed. The gain
Gcs can be adjusted by the value change of the Rcs3 resistor.
The internal Vcs voltage should be set to the output voltage
droop in applications with a DC load line requirement.
In order to recover the inductor DCR voltage drop current
signal, the pole frequency in the CSCOMP filter should be
set equal to the zero from the output inductor, that means
C
CS1
) C
CS2
+
L
DCR @ R
CS
(eq. 5)
Ccs1 and Ccs2 are in parallel to allow for a fine tuning of
the time constant using commonly available values. In
applications with a droop voltage V
DROOP
, the DC load line
LL can be obtained by
LL +
V
DROOP
I
OUT
+
0.5
ǒ
V
CSREF
* V
CSCOMP
Ǔ
I
OUT
(eq. 6)
+ 0.5 @
R
CS
R
CS3
@ DCR
NCP81252
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14
Over Current Protection
The NCP81252 provides two different types of current
limit protection. Current limits are programmed with a
resistor RILIM between the CSCOMP pin and the ILIM pin.
The current from the ILIM pin to this resistor is then
compared to two internal currents (10 mA and 15 mA)
corresponding to two different current limit thresholds ILIM
and ILIM_Fast (150% of ILIM level). If the ILIM pin
current exceeds the 10 mA level, an internal latch−off timer
starts. The controller shuts down if the fault is not removed
after 50 ms. If the current into the pin exceeds 15 mA the
controller will shut down immediately. To recover from an
OCP fault the EN pin must be cycled low.
The value of RILIM can be designed using the following
equation with a required over current protection threshold
ILIM and a known current−sense network.
R
ILIM
+
V
CS
@I
LIM
10 m
+
R
CS
R
CS3
@ I
LIM_PK
@ DCR @ 10
5
(eq. 7)
+
R
CS
R
CS3
@
ǒ
I
LIM
)
ǒ
V
IN
* V
OUT
Ǔ
@ V
OUT
2 @ L @ F
SW
@ V
IN
Ǔ
@ DCR @ 10
5
ICC_MAX
A resistor connected from IMAX pin to ground sets
ICC_MAX value at startup. A 10 mA current is sourced from
this pin to generate a voltage on the program resistor. The
resistor value can be determined by the following equation.
The resistor value should be no less than 10 k.
ICC_MAX +
R
ICCMAX
@ 10 m @ 64
2
+ R
ICCMAX
@ 3.2 @ 10
−4
(eq. 8)
IOUT
The IOUT pin sources a current equal to the ILIM sink
current gained by the IOUT Current Gain (10 typ.). The
voltage of the IOUT pin is monitored by the internal A/D
converter and should be scaled with an external resistor to
ground such that a load equal to ICCMAX generates a 2 V
signal on IOUT. A pull−up resistor to 5 V V
CC
can be used
to offset the IOUT signal positive if needed.
R
IOUT
+
2
10 @ V
CS
@ICC_MAX
@ R
ILIM
(eq. 9)
+
1
5 @
R
CS
R
CS3
@ ICC_MAX @ DCR
@ R
ILIM
Input UVLO Protection
NCP81252 monitors supply voltages at the VCC pin and
the VIN pins in order to provide under voltage protection. If
either supply drops below its threshold, the controller will
shut down the outputs. Upon recovery of the supplies, the
controller reenters its startup sequence, and soft start begins.
Output Under−Voltage Protection
The output voltage is monitored by a dedicated
differential amplifier. If the output falls below target by
more than “Under Voltage Threshold below DAC−Droop”,
the UVL comparator sends the VR_RDY signal low.
Output Over−Voltage Protection
During normal operation the output voltage is monitored
at the differential inputs VSP and VSN. If the output voltage
exceeds the DAC voltage by “Over Voltage Threshold above
DAC”, GH will be forced low, and GL will go high. After the
OVP trips, the DAC ramps slowly down to zero to avoid a
negative output voltage spike during shutdown. If the
DAC+OVP Threshold drops below the output, GL will
again go high, and will toggle between low and high as the
output voltage follows the DAC+OVP Threshold down.
When the DAC gets to zero, the GH will be held low and the
GL will remain high. To reset the part, the EN pin must be
cycled low. During soft−start, the OVP threshold is set to
2.9 V. This allows the controller to start up without false
triggering the OVP.
(a) Normal Operation Mode
(b) During Start Up
Figure 8. Function of Over Voltage Protection
NCP81252
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15
Temperature Sense and Thermal Alert
The NCP81252 provides an external temperature sense
and a thermal alert in normal operation mode. The
temperature sense and thermal alert circuit diagram is shown
in Figure 9. A precision current I
TSENSE
is sourced out the
output of the TSENSE pin to generate a voltage across the
temperature sense network, which consists of a NTC
thermistor R_NTC (100 kW typ.), two resistors R_COMP1
(0 W typ.) and R_COMP2 (8.2 kW typ.), and a filter
capacitor C_Filter (0.1 mF typ.). The voltage on the
temperature sense input is sampled by the internal A/D
converter and then digitally converted to temperature and
stored in SVID register 17h. Usually the thermistor is placed
close to a hot spot like inductor or NCP81252 itself. A 100k
NTC thermistor similar to the Murata
NCP15WF104D03RC should be used. The NCP81252 also
monitors the voltage at the TSENSE pin and compares the
voltage to internal thresholds and assert ALERT# or
VRHOT# once it trips the thresholds. The DC voltage at
TSENSE pin can be calculated by
V
TSENSE
+ I
TSENSE
@ ǒR
COMP1
)
R
COMP2
@ R
NTC_T
R
COMP2
) R
NTC_T
Ǔ
(eq. 10)
R
NTC_T
is the resistance of R_NTC at an absolute
temperature T, which is obtained by
R
NTC_T
+ R
NTC_T
0
@ exp
ǒ
B @
ǒ
1
T
*
1
T
0
Ǔ
Ǔ
(eq. 11)
where R
NTC_T0
is a known resistance of R_NTC at an
absolute temperature T
0
, and B is the B−constant of R_NTC.
34
TSENSE
3
ALERT#
R_NTC
R_COMP1
3.3V
ALERT#
Thermal
Management
R_COMP2
C_Filter
1
VRHOT#
VRHOT#
Figure 9. Temperature Sense and Thermal Alert Circuit Diagram

NCP81252MNTXG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Voltage Regulators SINGLE-PHASE VOLTAGE RE
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