NCP81252
www.onsemi.com
16
LAYOUT GUIDELINES
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction. Electrical
layout guidelines are:
− Power Paths: Use wide and short traces for power
paths (such as VIN, VOUT, SW, and PGND) to reduce
parasitic inductance and high−frequency loop area. It is
also good for efficiency improvement.
− Power Supply Decoupling: The device should be well
decoupled by input capacitors and input loop area
should be as small as possible to reduce parasitic
inductance, input voltage spike, and noise emission.
Usually, a small low−ESL MLCC is placed very close
to VIN and PGND pins.
− VCC Decoupling: Place decoupling caps as close as
possible to the controller VCC and VCCP pins. The
filter resistor at VCC pin should be not higher than
2.2 W to prevent large voltage drop.
− Switching Node: SW node should be a copper pour,
but compact because it is also a noise source.
− Bootstrap: The bootstrap cap and an option resistor
need to be very close and directly connected between
pin 8 (BST) and pin 10 (SW). No need to externally
connect pin 10 to SW node because it has been
internally connected to other SW pins.
− Ground: It would be good to have separated ground
planes for PGND and GND and connect the two planes
at one point. Directly connect GND pin to the exposed
pad and then connect to GND ground plane through
vias.
− Voltage Sense: Use Kelvin sense pair and arrange a
“quiet” path for the differential output voltage sense.
− Current Sense: Careful layout for current sensing is
critical for jitter minimization, accurate current
limiting, and IOUT reporting. The filter cap from
CSCOMP to CSREF should be close to the controller.
The temperature compensating thermistor should be
placed as close as possible to the inductor. The wiring
path should be kept as short as possible and well away
from the switch node.
− Compensation Network: The small feedback cap from
COMP to FB should be as close to the controller as
possible. Keep the FB traces short to minimize their
capacitance to ground.
− SVID Bus: The Serial VID bus is a high speed data bus
and the bus routing should be done to limit noise
coupling from the switching node. The signals should
be routed with the Alert# line in between the SVID
clock and SVID data lines. The SVID lines must be
ground referenced and each line’s width and spacing
should be such that they have nominal 50 W impedance
with the board stackup.
Thermal Layout Considerations
Good thermal layout helps high power dissipation from a
small package with reduced temperature rise. Thermal
layout guidelines are:
− The exposed pads must be well soldered on the board.
− A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
− More free vias are welcome to be around IC and
underneath the exposed pads to connect the inner
ground layers to reduce thermal impedance.
− Use large area copper pour to help thermal conduction
and radiation.
− Do not put the inductor to be too close to the IC, thus
the heat sources are distributed.
