9
FN6855.1
April 23, 2010
ISL6115AEVAL1Z Board
The ISL6115AEVAL1Z is default provided as a +12V
high side switch controller with the CR level set at
~2.5A. See Figure 11 for ISL6115AEVAL1Z schematic
and Table 3 for BOM. Bias and load connection points
are provided along with test points for each IC pin.
With J1 installed the ISL6115A will be biased from the
+12V supply (V
IN
) being switched. Connect the load to
VLOAD+. PWRON pin pulls high internally enabling the
ISL6115A if not driven low via PWRON test point or J2.
With R
3
= 1.24kΩ the CR Vth is set to 24.8mV and
with the 10mΩ sense resistor (R
1
) the
ISL6115AEVAL1Z has a nominal CR level of 2.5~A. The
0.01µF delay time to latch-off capacitor results in a
nominal 1ms before latch-off of output after an OC
event.
Reconfiguring the ISL6115AEVAL1Z board for a higher
CR level can be done by changing the R
SENSE
and/or
R
ISET
resistor values as the provided FET is rated for a
much higher current.
FIGURE 14. ISL6115AEVAL1Z HIGH SIDE SWITCH APPLICATION and PHOTOGRAPH
5
6
8
7
4
3
2
1
ISL6115A
Q1
R3
R2
C1
C3
R4
J1
V
BIAS
VIN
+12V
C2
R1
PWRON
V
BIAS
AGND
VLOAD+
U1
VOUT
C
TIM
J2
PGOOD
TABLE 3. BILL OF MATERIALS, ISL6115AEVAL1Z
COMPONENT
DESIGNATOR COMPONENT NAME COMPONENT DESCRIPTION
U1 ISL6115A Intersil
Q1 N-FET 11.5mΩ, 30V, 11.5A Logic Level N-Channel Power MOSFET or equivalent
R1 Load Current Sense Resistor WSL-2512 10mΩ 1W Metal Strip Resistor
R2 Gate Stability Resistor 20Ω 0603 Chip Resistor
R3 Overcurrent Voltage Threshold Set
Resistor
1.24kΩ 0603 Chip Resistor (Vth = 24.8mV)
R4 PGOOD Pull up Resistor 10kΩ 0603 Chip Resistor
C1 Gate Timing Capacitor 0.001µF 0402 Chip Capacitor (<2ms)
C2 IC Decoupling Capacitor 0.1µF 0402 Chip Capacitor
C3 Time Delay Set Capacitor 0.01µF 0402 Chip Capacitor (1ms)
J1 Bias Voltage Selection Jumper Install if switched rail voltage is = +12V. Remove and provide separate
+12V bias voltage to U2 via V
BIAS
if ISL6116, ISL6117 or ISL6120 is
being evaluated.
J2 PWRON Disable Install J2 to disable U2. Connects PWRON to GND.
ISL6115A
