LTC4215CUFD-1#PBF Datasheet LTC4215CUFD-3#PBF, LTC4215CUFD-1#PBF, LTC4215IUFD-1#PBF | P13-P15

LTC4215-1/LTC4215-3

421513fc

The MOSFET is turned on by charging up the GATE with

a 20µA current source. When the GATE voltage reaches

the MOSFET threshold voltage, the MOSFET begins to

turn on and the SOURCE voltage then follows the GATE

voltage as it increases.

When the MOSFET is turning on, it ramps inrush current

up linearly at a dI/dt rate selected by capacitor C

. Once

the inrush current reaches the limit set by the FB pin, the

dI/dt ramp stops and the inrush current follows the fold-

back proﬁ le as shown in Figure 2. The TIMER capacitor

integrates at 100µA during start-up and once it reaches its

thr eshold of 1. 235 V, the par t chec ks to s e e i f it i s in curr ent

limit, which indicates that it has started up into a short-

circuit condition. If this is the case, the overcurrent fault

bit, D2 in Table 5, is set and the part turns off. If the part

is not in current limit, the 25mV circuit breaker is armed

and the current limit is switched to 75mV. Alternately an

internal 100ms start-up timer may be selected by tying

the TIMER pin to INTV

As the SOURCE voltage rises, the FB pin follows as set by

R7 and R8. Once FB crosses its 1.235V threshold, and the

start-up timer has expired, the GPIO1 pin, if conﬁ gured

to indicate power-good, ceases to pull low and indicates

that power is now good. Alternately bit C3 can be read

to check power-good status, where a zero indicates that

power is good.

Figure 2. Power-Up Waveforms

If R6 and C1 are employed for a constant current during

start-up, which produces a constant dV/dt at the output,

a 20µA pull-up current from the gate pin slews the gate

upwards and the part is not in current limit. The start-up

TIMER may expire in this condition and an overcurrent

(OC) fault is not generated even though start-up has not

completed. Either the sense voltage increases to the

25mV CB threshold and generates an OC fault, or the FB

pin voltage crosses its 1.235V power good threshold and

is indicated in bit C3 as well as the GPIO1 pin if GPIO1 is

conﬁ gured to do so.

GATE Pin Voltage

A curve of GATE-to-SOURCE drive vs V

is shown in the

Typical Performance Characteristics. At minimum input

supply voltage of 2.9V, the minimum GATE-to-SOURCE

drive voltage is 4.7V. The GATE-to-SOURCE voltage is

clamped below 6.5V to protect the gates of logic level

N-channel MOSFETs.

Turn-Off Sequence

The GATE is turned off by a variety of conditions. A normal

turn-off is initiated by the ON pin going low or a serial bus

turn-off command. Additionally, several fault conditions

turn off the GATE. These include an input overvoltage

APPLICATIONS INFORMATION

+ 6V

GATE

OUT

GPIO1

(POWER GOOD)

LOAD

• R

SENSE

25mV

10mV

LIMITED

4215 F02

TIMER

EXPIRES

STARTUP

LTC4215-1/LTC4215-3

421513fc

(OV pin), input undervoltage (UV pin), overcurrent circuit

breaker (SENSE

–

pin), or EN transitioning high. Writing

a logic one into the UV, OV or OC fault bits (D0-D2 in

Table 5) also latches off the GATE if their auto-retry bits

are set to false.

Normally the MOSFET is turned off with a 1mA current

pulling down the GATE pin to ground. With the MOSFET

turned off, the SOURCE and FB voltages drop as CL dis-

charges. When the FB voltage crosses below its threshold,

GPIO1 may be conﬁ gured to pull low to indicate that the

output power is no longer good.

If the V

pin falls below 2.74V for greater than 2µs or

INTV

drops below 2.60V for greater than 1µs, a fast shut

down of the MOSFET is initiated. The GATE pin is pulled

down with a 450mA current to the SOURCE pin.

Overcurrent Fault

The LTC4215-1/LTC4215-3 feature an adjustable current

limit that protects against short circuits or excessive load

current. An overcurrent fault occurs when the circuit

breaker 25mV threshold has been exceeded for longer than

the 20µs (LTC4215-1) or 420µs (LTC4215-3) time-out delay.

Current limiting begins immediately when the current sense

voltage between the V

and SENSE pins reaches 75mV.

The GATE pin is then brought down and regulated in order

to limit the current sense voltage to 75mV. When the 20µs

(LTC4215-1) or 420µs (LTC4215-3) circuit breaker time

out has expired, the external MOSFET is turned off and the

overcurrent fault bit D2 is set.

After the MOSFET is turned off, the TIMER capacitor

begins discharging with a 2µA pull-down current. When

the TIMER pin reaches its 0.2V threshold the MOSFET is

allowed to turn on again if the overcurrent fault has been

cleared. However, if the overcurrent auto-retry bit, A2 has

been set then the MOSFET turns on again automatically

without resetting the overcurrent fault. Use a minimum

value of 10nF for C

. If the TIMER pin is bypassed by tying

it to INTV

, the part is allowed to turn on again after an

internal 5 second timer has expired, in the same manner

as the TIMER pin passing its 0.2V threshold.

Overvoltage Fault

An overvoltage fault occurs when either the OV pin rises

above its 1.235V threshold, or the V

pin rises above its

15.6V threshold, for more than 2µs. This shuts off the GATE

with a 1mA current to ground and sets the overvoltage

present bit C0 and the overvoltage fault bit D0. If the pin

subsequently falls back below the threshold for 100ms,

the GATE is allowed to turn on again unless overvoltage

auto-retry has been disabled by clearing bit A0.

Undervoltage Fault

An undervoltage fault occurs when the UV pin falls below

its 1.235V threshold for more than 2µs. This turns off the

GATE with a 1mA current to ground and sets undervoltage

present bit C1 and undervoltage fault bit D1. If the UV pin

subsequently rises above the threshold for 100ms, the

GATE is turned on again unless undervoltage auto-retry

has been disabled by clearing bit A1. When power is ap-

plied to the device, if UV is below its 1.235V threshold after

INTV

crosses its 2.64V undervoltage lockout threshold,

an undervoltage fault is logged in the fault register.

Figure 3. Short-Circuit Waveforms

APPLICATIONS INFORMATION

GATE

10V/DIV

SOURCE

10V/DIV

LOAD

10A/DIV

5µs/DIV

4215 F03

= 5mΩ

= 0

SHORT

= 1Ω

R6 = 30k

C1 = 0.1µF

LTC4215-1/LTC4215-3

421513fc

Board Present Change of State

Whenever the EN pin toggles, bit D4 is set to indicate a

change of state. When the EN pin goes high, indicating

board removal, the GATE turns off immediately (with a 1mA

current to ground) and clears the board present bit, C4. If

the EN pin is pulled low, indicating a board insertion, all

fault bits except D4 are cleared and enable bit, C4, is set.

If the EN pin remains low for 100ms the state of the ON

pin is captured in ‘FET On’ control bit A3. This turns the

switch on if the ON pin is tied high. There is an internal

10µA pull-up current source on the EN pin.

If the system shuts down due to a fault, it may be desirable

to restart the system simply by removing and reinserting

a load card. In cases where the LTC4215-1/LTC4215-3 and

the switch reside on a backplane or midplane and the load

resides on a plug-in card, the EN pin detects when the

p l u g - i n c a r d i s r e mo v e d . F i g ur e 4 s h o w s a n ex a m p l e w h e r e

the EN pin is used to detect insertion. Once the plug-in

card is reinserted the fault register is cleared (except for

D4). After 100ms the state of the ON pin is latched into

bit A3 of the control register. At this point the system

starts up again.

If a connection sense on the plug-in card is driving the EN

pin, insertion or removal of the card may cause the pin

voltage to bounce. This results in clearing the fault register

when the card is removed. The pin may be debounced

using a ﬁ lter capacitor, C

, on the EN pin as shown in

Figure 4. The ﬁ lter time is given by:

FILTER

= C

• 123 [ms/µF]

FET Short Fault

A FET short fault is reported if the data converter mea-

sures a current sense voltage greater than or equal to

1.6mV while the GATE is turned off. This condition sets

FET short fault bit D5.

Power Bad Fault

A power bad fault is reported if the FB pin voltage drops

below its 1.235V threshold for more than 2µs when the

GATE is high. This pulls the GPIO1 pin low immediately

when conﬁ gured as power-good, and sets power-bad pres-

ent bit, C3, and power bad fault bit D3. A circuit prevents

power-bad faults if the GATE-to-SOURCE voltage is low,

eliminating false power-bad faults during power-up or

power-down. If the FB pin voltage subsequently rises back

above the threshold, a power-good conﬁ gured GPIO1 pin

returns to a high impedance state and bit C3 is reset.

Fault Alerts

When any of the fault bits in FAULT register D are set, an

optional bus alert is generated if the appropriate bit in the

ALERT register B has been set. This allows only selected

faults to generate alerts. At power-up the default state is

to not alert on faults and the GPIO2 pin is high. If an alert

is enabled, the corresponding fault causes the GPIO2 pin

to pull low. After the bus master controller broadcasts

the Alert Response Address, the LTC4215-1/LTC4215-3

respond with their addresses on the SDA line and releases

GPIO2 as shown in Table 6. If there is a collision between

two LTC4215-1/LTC4215-3s responding with their ad-

dresses simultaneously, then the device with the lower

address wins arbitration and responds ﬁ rst. The GPIO2

line is also released if the device is addressed by the bus

master if GPIO2 is pulled low due to an alert.

Figure 4. Plug-In Card Insertion/Removal

APPLICATIONS INFORMATION

–

1.235V

GND

MOTHERBOARD

CONNECTOR PLUG-IN

CARD

SOURCE

OUT

LTC4215-1

LOAD

4215 F04

10µA

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

LTC4215CUFD-1#PBF

Mfr. #:

Buy LTC4215CUFD-1#PBF

Manufacturer:

Analog Devices Inc.

Description:

Hot Swap Voltage Controllers Hot Swap Contr. w/ADC and I2C, 3GPIOs

Lifecycle:

New from this manufacturer.

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LTC4215CUFD-1#PBF

LTC4215CUFD-1#PBF

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