LTC4215CUFD-1#PBF Datasheet LTC4215CUFD-3#PBF, LTC4215CUFD-1#PBF, LTC4215IUFD-1#PBF | P16-P18

LTC4215-1/LTC4215-3

421513fc

Once the GPIO2 signal has been released for one fault, it

is not pulled low again until the FAULT register indicates a

different fault has occurred or the original fault is cleared

and it occurs again. Note that this means repeated or con-

tinuing faults do not generate alerts until the associated

FAULT register bit has been cleared.

The GPIO2 pin may also be used as a general purpose

output by setting or resetting bit D6. When D6 is set,

GPIO2 will pull low, and when D6 is reset (default) GPIO2

will be high or pulled low due to an alert. The LTC4215-1/

LTC4215-3 will not respond to the alert response address

if the GPIO2 pin is being pulled low due to bit D6 being

set. See Figure 12 for a schematic detailing the behavior

of the GPIO2 pin.

Resetting Faults

Faults are reset with any of the following conditions. First,

a serial bus command writing zeros to the FAULT register

D bits 0-5 clears the associated faults. Second, FAULT

off by the ON pin or bit A3 going from high to low, if the

UV pin is brought below its 0.4V reset threshold for 2µs,

or if INTV

falls below its 2.64V undervoltage lockout

threshold. Finally, when EN is brought from high to low,

only FAULT bits D0-D3 and D5 are cleared, and bit D4,

w h i c h i n d i c a t e s a E N c h a n g e o f s t a t e , i s s e t . N o t e t h a t f a u l t s

that are still present, as indicated in STATUS Register C,

cannot be cleared.

The FAULT register is not cleared when auto-retrying.

When auto-retry is disabled the existence of a D0, D1

or D2 fault keeps the switch off. As soon as the fault is

cleared, the switch turns on. If auto-retry is enabled, then

a high value in C0 or C1 holds the switch off and the fault

are cleared by removal of the fault condition, the switch is

allowed to turn on again. The LTC4215-1/LTC4215-3 will

set bit D2 and turn off in the event of an overcurrent fault,

preventing it from remaining in an overcurrent condition.

If conﬁ gured to auto-retry, the LTC4215-1/LTC4215-3

will continually attempt to restart after cool-down cycles

until it succeeds in starting up without generating an

overcurrent fault.

Data Converter

The LTC4215-1/LTC4215-3 incorporate an 8-bit ΔΣ A/D

converter that continuously monitors three different volt-

ages. The ΔΣ a r c h i t e c t u r e i n h e r e n t l y a v e r a g e s s i g n a l n o i s e

during the measurement period. The SOURCE pin has a

1/12.5 resistive divider to monitor a full scale voltage of

15.4V with 60mV resolution. The ADIN pin is monitored

with a 1.235V full scale and 4.82mV resolution, and the

voltage between the V

and SENSE pins is monitored

with a 38.6mV full scale and 151µV resolution.

Results from each conversion are stored in registers E

(Sense), F (Source) and G (ADIN), as seen in Tables 6-8,

and are updated 10 times per second. Setting CONTROL

converter so that registers E, F, and G may be written to

and read from for software testing.

Conﬁ guring the GPIO Pins

Table 2 describes the possible states of the GPIO1 pin

using the control register bits A6 and A7. At power-up, the

default state is for the GPIO1 pin to be a general purpose

output with output value set by bit B6 (default 1 = GPIO1

Hi-Z). Other applications for the GPIO1 pin are to go high

impedance when power is good (FB pin greater than

1.235V), pull down when power is good, and a general

purpose input. Digital input information can be read from

bit C6 (Table 4).

Table 3 is used to conﬁ gure the GPIO2 pin as a fault

alert output (See Fault Alerts) and also can be used as a

general purpose output and a general purpose input. By

default the GPIO2 pin is a general purpose output in the

high-impedance state as set by bit D6 (default 0 = GPIO2

Hi-Z, Table 5). Digital input information can be read from

bit C5 (Table 4).

The GPIO3 pin is a general purpose output/input that

defaults to output-low as set by bit D7 (default 1 = GPIO3

pulled low, Table 5). Digital input information can be read

from bit C2 (Table 4).

APPLICATIONS INFORMATION

LTC4215-1/LTC4215-3

421513fc

Current Limit Stability

For many applications the LTC4215-1/LTC4215-3 current

limits will be stable without additional components. How-

ever there are certain conditions where additional compo-

nents may be needed to improve stability. The dominant

pole of the current limit circuit is set by the capacitance

and resistance at the gate of the external MOSFET, and

larger gate capacitance makes the current limit loop more

stable. Usually a total of 8nF gate to source capacitance

is sufﬁ cient for stability and is typically provided by in-

herent MOSFET C

, however the stability of the loop is

degraded by increasing R

SENSE

or by reducing the size of

the resistor on a gate RC network if one is used, which

may require additional gate to source capacitance. Board

level short-circuit testing is highly recommended as board

layout can also affect transient performance, for stability

testing the worst case condition for current limit stabil-

ity occurs when the output is shorted to ground after a

normal start-up.

There are two possible parasitic oscillations when the

MOSFET operates as a source follower when ramping

at power-up or during current limiting. The ﬁ rst type of

oscillation occurs at high frequencies, typically above

1MHz. This high frequency oscillation is easily damped

with R5 as shown in Figure 1. In some applications, one

may ﬁ nd that R5 helps in short-circuit transient recovery

as well. However, too large of an R5 value will slow down

the turn-off time. The recommended R5 range is between

5 and 500.

The second type of source follower oscillation occurs

at frequencies between 200kHz and 800kHz due to load

capacitance being between 0.2µF and 9µF, the presence

of R5 resistance, the absence of a drain bypass capacitor,

a combination of bus wiring inductance and bus supply

o u t p u t i m p e d a n c e . To p r e v e n t t h e s e c o n d t y p e o f o s c i l l a t i o n

avoid load capacitance below 10µF, alternately connect an

external capacitor from the MOSFET gate to ground with

a value greater than 1.5nF.

Supply Transients

The LTC4215-1/LTC4215-3 are designed to ride through

s u p p l y t r a n s i e n t s c a u s e d b y l o a d s t e p s . I f t h e r e i s a s h o r t e d

load and the parasitic inductance back to the supply is

greater than 0.5µH, there is a chance that the supply col-

lapses before the active current limit circuit brings down

the GATE pin. If this occurs, the undervoltage monitors

pull the GATE pin low. The undervoltage lockout circuit

has a 2µs ﬁ lter time after V

drops below 2.74V. The UV

pin reacts in 2µs to shut the GATE off, but it is recom-

mended to add a ﬁ lter capacitor C

to prevent unwanted

shutdown caused by a transient. Eventually either the UV

pin or undervoltage lockout responds to bring the current

under control before the supply completely collapses.

Supply Transient Protection

The LTC4215-1/LTC4215-3 are safe from damage with

supply voltages up to 24V. However, spikes above 24V

may damage the part. During a short-circuit condition,

Figure 5. Recommended Layout

APPLICATIONS INFORMATION

GND

SDAO

GPIO1

INTV

TIMER

ADIN

GPIO3

ADR1

SENSE

–

GATE

SOURCE

SDAI

SCL

GPIO2

ADR0

SENSE RESISTOR R

LTC4215-1

LOAD

4215 F05

LOAD

LTC4215-1/LTC4215-3

421513fc

large changes in current ﬂ owing through power supply

traces may cause inductive voltage spikes which exceed

24V. To minimize such spikes, the power trace inductance

should be minimized by using wider traces or heavier

trace plating. Also, a snubber circuit dampens inductive

voltage spikes. Build a snubber by using a 100Ω resistor

in series with a 0.1µF capacitor between V

and GND.

A surge suppressor, Z1 in Figure 1, at the input can also

prevent damage from voltage surges.

Design Example

As a design example, take the following speciﬁ cations:

= 12V, I

MAX

= 5A, I

INRUSH

= 1A, dI/dt

INRUSH

= 10A/ms,

= 330µF, V

UV(ON)

= 10.75V, V

OV(OFF)

= 14.0V, V

PWRGD(UP)

= 11.6V, and I

C ADDRESS = 1001011. This completed

design is shown in Figure 1.

Selection of the sense resistor, R

, is set by the overcurrent

threshold of 25mV:

25mV

MAX

= 0.005

The MOSFET is sized to handle the power dissipation dur-

ing inrush when output capacitor C

is being charged. A

method to determine power dissipation during inrush is

based on the principle that:

Energy in C

= Energy in Q1

This uses:

Energy in C

0.33mF

()

or 0.024 Joules. Calculate the time it takes to charge up

OUT

STARTUP

= C

•

INRUSH

= 0.33mF •

12V

= 4ms

The power dissipated in the MOSFET:

DISS

Energyin C

STARTUP

= 6W

The SOA (safe operating area) curves of candidate MOSFETs

must be evaluated to ensure that the heat capacity of the

package tolerates 6W for 4ms. The SOA curves of the

Fairchild FDC653N provide for 2A at 12V (24W) for 10ms,

satisfying this requirement. Since the FDC653N has less

than 8nF of gate capacitance and we are using a GATE

RC network, the short circuit stability of the current limit

should be checked and improved by adding a capacitor

from GATE to SOURCE if needed.

The inrush current is set to 1A using C1:

C1= C

•

GATE

INRUSH

C1= 0.33mF •

20µA

or C1= 6.8nF

The inrush dI/dt is set to 10A/ms using C

dI / dt













• 0.0375 •

SENSE

10µA

10000

• 0.0375 •

5m

= 7.5nF

For a start-up time of 4ms with a 2x safety margin we

choose:

TIMER

= 2•

STARTUP

12.3ms/µF

+ C

•10

TIMER

8ms

12.3ms/µF

+ 7.5nF • 10  0.68µF

Note the minimum value of C

TIMER

is 10nF, and each 1nF

of soft-start capacitance needs 10nF of TIMER capaci-

tance/time during start-up.

The UV and OV resistor string values can be solved in the

following method. First pick R3 based on I

STRING

being

APPLICATIONS INFORMATION

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

LTC4215CUFD-1#PBF

Mfr. #:

Buy LTC4215CUFD-1#PBF

Manufacturer:

Analog Devices Inc.

Description:

Hot Swap Voltage Controllers Hot Swap Contr. w/ADC and I2C, 3GPIOs

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

LTC4215CUFD-1#PBF

LTC4215CUFD-1#PBF

Products related to this Datasheet