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LTC4215CUFD-1#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
LTC4215-1/LTC4215-3
22
421513fc
master acknowledges the transmitted data byte, as in a
Read Word command, Figure 10, the LTC4215-1/LTC4215-3
repeat the requested register as the second data byte.
Alert Response Protocol
When any of the fault bits in FAULT register D are set, an
optional bus alert is generated if the appropriate bit in
the ALERT register B is also set. If an alert is enabled, the
corresponding fault causes the GPIO2 pin to pull low. After
the bus master controller broadcasts the Alert Response
Address, the LTC4215-1/LTC4215-3 respond with their
address on the SDA line and then release GPIO2 as shown
in Figure 11. The GPIO2 line is also released if the device
is addressed by the bus master. The GPIO2 signal is not
pulled low again until the FAULT register indicates a differ-
ent fault has occurred or the original fault is cleared and it
occur s again. Note that this means repeated or continuing
faults do not generate alerts until the associated FAULT
register bit has been cleared.
APPLICATIONS INFORMATION
Table 1. LTC4215-1/LTC4215-3 Device Addressing
DESCRIPTION*
DEVICE
ADDRESS DEVICE ADDRESS
LTC4215-1/LTC4215-3
ADDRESS PINS
h 76543210ADR1 ADR0
Mass Write BE 10111110 X X
Alert Response 19 00011001 X X
8 90 1001000X NC L
9 92 1001001X H NC
10 94 1001010X NC NC
11 96 1001011X NC H
12 98 1001100X L L
13 9A 1001101X H H
14 9C 1001110X L NC
15 9E 1001111X L H
25 B2 1011001X H L
*Subset of LTC4215 addresses
LTC4215-1/LTC4215-3
23
421513fc
Table 2. CONTROL Register A (00h)—Read/Write
BIT NAME OPERATION
A7:6 GPIO1 Confi gure
FUNCTION A6 A7 GPIO PIN
Power Good 0 0 GPIO = C3
Power Good 0 1 GPIO = C3
General Purpose Output (Default) 1 0 GPIO = B6
General Purpose Input 1 1 C6 = GPIO1
A5 Test Mode Enable Enables Test Mode to Disable the ADC; 1 = ADC Disable, 0 = ADC Enable (Default)
A4 Mass Write Enable Allows Mass Write Addressing; 1 = Mass Write Enabled (Default), 0 = Mass Write Disabled
A3 FET On Control On Control Bit Latches the State of the ON Pin at the End of the Debounce Delay; 1 = FET On, 0 = FET Off
A2 Overcurrent
Auto-Retry
Overcurrent Auto-Retry Bit; 1 = Auto-Retry After Overcurrent, 0 = Latch Off After Overcurrent (Default)
A1 Undervoltage
Auto-Retry
Undervoltage Auto-Retry; 1 = Auto-Retry After Undervoltage (Default), 0 = Latch Off After Undervoltage
A0 Overvoltage
Auto-Retry
Overvoltage Auto-Retry; 1 = Auto-Retry After Overvoltage (Default), 0 = Latch Off After Overvoltage
Table 3. ALERT Register B (01h)—Read/Write
BIT NAME OPERATION
B7 Reserved Not Used
B6 GPIO1 Output Output Data Bit to GPIO1 Pin when Confi gured as Output. Defaults to 1
B5 FET Short Alert Enables Alert for FET Short Condition; 1 = Enable Alert, 0 = Disable Alert (Default)
B4 EN State
Change Alert
Enables Alert when EN Changes State; 1 = Enable Alert, 0 Disable Alert (Default)
B3 Power Bad
Alert
Enables Alert when Output Power is Bad; 1 = Enable Alert, 0 Disable Alert (Default)
B2 Overcurrent
Alert
Enables Alert for Overcurrent Condition; 1 = Enable Alert, 0 Disable Alert (Default)
B1 Undervoltage
Alert
Enables Alert for Undervoltage Condition; 1 = Enable Alert, 0 Disable Alert (Default)
B0 Overvoltage
Alert
Enables Alert for Overvoltage Condition; 1 = Enable Alert, 0 Disable Alert (Default)
APPLICATIONS INFORMATION
LTC4215-1/LTC4215-3
24
421513fc
Table 4. STATUS Register C (02h)—Read
BIT NAME OPERATION
C7 FET On 1 = FET On, 0 = FET Off
C6 GPIO1 Input Reports the State of the GPIO1 Pin; 1 = GPIO1 High, 0 = GPIO1 Low
C5 GPIO2 Input Reports the State of the GPIO2 Pin; 1 = GPIO2 High, 0 = GPIO2 Low
C4 EN Indicates if the LTC4215 is Enabled when EN is Low; 1 = EN Pin Low, 0 = EN Pin High
C3 Power Bad Indicates Power is Bad when FB is Low; 1 = FB Low, 0 = FB High
C2 GPIO3 Input Reports the State of the GPIO3 Pin; 1 = GPIO3 High, 0 = GPIO3 Low
C1 Undervoltage Indicates Input Undervoltage when UV is Low; 1 = UV Low, 0 = UV High
C0 Overvoltage Indicates V
DD
or OV Input Overvoltage when OV is High; 1 = OV High, 0 = OV Low
Table 5. FAULT Register D (03h)—Read/Write
BIT NAME OPERATION
D7 GPIO3 Output Sets the State of the GPIO3 Pin; 1 = GPIO3 Pulled Low (Default), 0 = GPIO3 High Impedance
D6 GPIO2 Output Sets the State of the GPIO2 Pin; 1 = GPIO2 Pulled Low, 0 = GPIO2 High Impedance (Default)
D5 FET Short Fault
Occurred
Indicates Potential FET Short was Detected when Measured Current Sense Volage Exceeded 1mV While FET was Off;
1 = FET is Shorted, 0 = FET is Good
D4 EN Changed
State
Indicates That the LTC4215 was Enabled or Disabled when EN Changed State; 1 = EN Changed State, 0 = EN Unchanged
D3 Power Bad
Fault Occurred
Indicates Power was Bad when FB when Low; 1 = FB was Low, 0 = FB was High
D2 Overcurrent
Fault Occurred
Indicates Overcurrent Fault Occured; 1 = Overcurrent Fault Occured, 0 = Not Overcurrent Faults
D1 Undervoltage
Fault Occurred
Indicates Input Undervoltage Fault Occured when UV went Low; 1 = UV was Low, 0 = UV was High
D0 Overvoltage
Fault Occurred
Indicates Input Overvoltage Fault Occured when OV went High; 1 = OV was High, 0 = OV was Low
Table 6. SENSE Register E (04h)—Read/Write
BIT NAME OPERATION
E7:0 SENSE Voltage Measurement Sense Voltage Data, 8-Bit Data with 151µV LSB and 38.45mV Full Scale
Table 7. SOURCE Register F (05h)—Read/Write
BIT NAME OPERATION
F7:0 SOURCE Voltage
Measurement
SOURCE Voltage Data, 8-Bit Data with 60.5mV LSB and 15.44V Full Scale
Table 8. ADIN Register G (06h)—Read/Write
BIT NAME OPERATION
G7:0 ADIN Voltage Measurement ADIN Voltage Data, 8-Bit Data with 4.82mV LSB and 1.23V Full Scale
APPLICATIONS INFORMATION
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

LTC4215CUFD-1#PBF

Mfr. #:
Buy LTC4215CUFD-1#PBF
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Hot Swap Contr. w/ADC and I2C, 3GPIOs
Lifecycle:
New from this manufacturer.
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