Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B | Page 13 of 20
RECEIVER TIMING MEASUREMENTS
A
NOTES
1. C
L
IS 20%, CERAMIC, SUR
FACE MOUN
T,
AND INCLUDES
PROBE/STR
A
Y
CA
P
ACI
T
ANCE < 2cm FROM DU
T
.
V
OUT
C
L
15pF
B
10355-030
RO
RE
V
ID
Figure 30. Receiver Timing Measurement
A
1.4V
1.0V
1.2V
RE INPUT
NOTES
1. C
L
IS 20% AND INCLUDES PROBE/STRAY
CAPACITANCE < 2cm FROM DUT.
2. R
L
IS 1% METAL FILM, SURFACE MOUNT, <2cm FROM DUT.
V
OUT
C
L
15pF
R
L
499Ω
B
10355-031
RO
RE
V
TEST
Figure 31. Receiver Enable/Disable Time
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
100MHz; 50% ± 1% DUTY CYCLE.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
V
OH
V
OL
0V
1/f0
INPUT
(V
A
– V
B
)
10355-032
0.5V
CC
0.5V
CC
0.5V
CC
0.5V
CC
1/f0
OUTPUT
(IDEAL)
V
OH
V
OL
OUTPUT
(ACTUAL)
t
c(n)
t
J(PER)
= |
t
c(n)
– 1f0|
Figure 32. Receiver Period Jitter Characteristics
NOTES
1. INPUT PULSE GENERATOR: 50MHz; 50% ± 5% DUTY CYCLE; t
R
, t
F
≤ 1ns.
2. MEASURED ON TEST EQUIPMENT WITH –3dB BANDWIDTH ≥ 1GHz.
t
RPHL
V
A
0.5V
CC
0.5V
CC
V
B
V
OH
V
OL
V
ID
V
OUT
0V
90%
10%
90%
10%
0V
t
F
t
RPLH
t
R
10355-033
Figure 33. Receiver Propagation and Rise/Fall Times
0.5V
CC
0.5V
CC
V
CC
0V
V
CC
0V
V
OL
V
OH
0.5V
CC
0.5V
CC
V
OH
– 0.5V
RE INPUT
(V
TEST
= V
CC
)
(A = 1V)
V
OUT
V
OUT
(V
TEST
= 0V)
(A = 1.4V)
10355-034
t
RPZH
t
RPZL
V
OL
+ 0.5V
t
RPHZ
t
RPLZ
NOTES
1. INPUT PULSE GENERATOR: 500kHz; 50% ± 5% DUTY CYCLE;
t
R
,
t
F
≤ 1ns.
Figure 34. Receiver Enable/Disable Times
NOTES
1. INPUT PULSE GENERATOR: AGILENT 8304A STIMULUS SYSTEM;
200Mbps; 2
15
– 1PRBS.
2. MEASURED USING TEK TDS6604 WITH TDSJIT3 SOFTWARE.
V
OH
V
OL
V
A
V
B
OUTPUT
INPUT
(PRBS)
t
J(PP)
0.5V
CC
0.5V
CC
10355-035
Figure 35. Receiver Peak-to-Peak Jitter Characteristics
ADN4691E/ADN4693E/ADN4696E/ADN4697E Data Sheet
Rev. B | Page 14 of 20
THEORY OF OPERATION
The ADN4691E/ADN4693E/ADN4696E/ADN4697E are trans-
ceivers for transmitting and receiving multipoint, low voltage
differential signaling (M-LVDS) at high speed (data rates up
to 200 Mbps). Each device has a differential line driver and a
differential line receiver, allowing each device to send and
receive data.
Multipoint LVDS expands on the established LVDS low voltage
differential signaling method by allowing bidirectional commu-
nication between more than two nodes. Up to 32 nodes can
connect on an M-LVDS bus.
HALF-DUPLEX/FULL-DUPLEX OPERATION
Half-duplex operation allows a transceiver to transmit or
receive, but not both at the same time. However, with full-
duplex operation, a transceiver can transmit and receive
simultaneously. The ADN4691E/ADN4696E are half-duplex
devices in which the driver and the receiver share differential
bus terminals. The ADN4693E/ADN4697E are full-duplex
devices that have dedicated driver output and receiver input
pins. Figure 37 and Figure 38 show typical half- and full-duplex
bus topologies, respectively, for M-LVDS.
THREE-STATE BUS CONNECTION
The outputs of the device can be placed in a high impedance
state by disabling the driver or receiver. This allows several
driver outputs to connect to a single M-LVDS bus. Note that, on
each bus line, only one driver can be enabled at a time, but
many receivers can be enabled at the same time.
The driver can be enabled or disabled using the driver enable
pin (DE). DE enables the driver outputs when taken high; when
taken low, DE puts the driver outputs into a high impedance state.
Similarly, an active low receiver enable pin (
RE
) controls the
receiver. Taking
RE
low enables the receiver, whereas taking it
high puts the receiver outputs into a high impedance state.
Truth tables for driver and receiver output states under various
conditions are shown in Table 10, Table 11, Table 12, and Table 13.
TRUTH TABLES
Table 9. Truth Table Abbreviations
Abbreviation Description
H High level
L
Low level
X Don’t care
I Indeterminate
Z High impedance (off)
NC Disconnected
Driver, Half-Duplex (ADN4691E/ADN4696E)
Table 10. Transmitting (See Table 9 for Abbreviations)
Power
Inputs Outputs
DE DI A B
Yes H H H L
Yes H L L H
Yes H NC L H
Yes L X Z Z
Yes NC X Z Z
≤1.5 V X X Z Z
Driver, Full-Duplex (ADN4693E/ADN4697E)
Table 11. Transmitting (See Table 9 for Abbreviations)
Power
Inputs Outputs
DE DI Y Z
Yes H H H L
Yes H L L H
Yes H NC L H
Yes L X Z Z
Yes NC X Z Z
≤1.5 V X X Z Z
Type 1 Receiver (ADN4691E/ADN4693E)
Table 12. Receiving (see Table 9 for Abbreviations)
Power
Inputs Output
A − B
RE
RO
Yes 50 mV L H
Yes ≤−50 mV L L
Yes −50 mV < A − B < 50 mV L
I
Yes NC L I
Yes X H
Z
Yes X NC Z
No X X Z
Type 2 Receiver (ADN4696E/ADN4697E)
Table 13. Receiving (See Table 9 for Abbreviations)
Power
Inputs
Output
A − B
RE
RO
Yes 150 mV L
H
Yes ≤50 mV L L
Yes 50 mV < A B < 150 mV L
I
Yes NC L L
Yes X H
Z
Yes X NC Z
No X X Z
Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B | Page 15 of 20
GLITCH-FREE POWER-UP/POWER-DOWN
To minimize disruption to the bus when adding nodes, the
M-LVDS outputs of the device are kept glitch-free when the
device is powering up or down. This feature allows insertion of
devices onto a live M-LVDS bus because the bus outputs are not
switched on before the device is fully powered. In addition, all
outputs are placed in a high impedance state when the device is
powered off.
FAULT CONDITIONS
The ADN4691E/ADN4693E/ADN4696E/ADN4697E contain
short-circuit current protection that protects the device under
fault conditions in the case of short circuits on the bus. This
protection limits the current in a fault condition to 24 mA at
the transmitter outputs for short-circuit faults between 1 V
and 3.4 V. Any network fault must clear to avoid data
transmission errors and to ensure reliable operation of the data
network and any devices that are connected to the network.
RECEIVER INPUT THRESHOLDS/FAIL-SAFE
Two receiver types are available, both of which incorporate
protection against short circuits.
The Type 1 receivers of the ADN4691E/ADN4693E incorporate
25 mV of hysteresis. This ensures that slow changing signals or
a loss of input does not result in oscillation of the receiver output.
Type 1 receiver thresholds are ±50 mV; therefore, the state of the
receiver output is indeterminate if the differential between A and
B is about 0 V. This state occurs if the bus is idle (approximately 0 V
on both A and B), with no drivers enabled on the attached nodes.
Type 2 receivers (ADN4696E/ADN4697E) have an open circuit
and bus-idle fail-safe. The input threshold is offset by 100 mV so
a logic low is present on the receiver output when the bus is idle
or when the receiver inputs are open.
The different receiver thresholds for the two receiver types are
illustrated in Figure 36. See Tabl e 12 and Table 13 for receiver
output states under various conditions.
TYPE 1 RECEIVER
OUTPUT
LOGIC 1
LOGIC 0
DIFFERENTIAL INPUT VOLTAGE (V
IA
– V
IB
) [V]
0.25
0.15
0.05
–0.05
–0.15
0
TYPE 2 RECEIVER
OUTPUT
LOGIC 1
LOGIC 0
UNDEFINED
10355-036
UNDEFINED
Figure 36. Input Threshold Voltages

ADN4691EBRZ-RL7

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
LVDS Interface IC MLVDS Xcvr,HD,200M Type 1 Rx,EnhancedESD
Lifecycle:
New from this manufacturer.
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