Data Sheet ADN4691E/ADN4693E/ADN4696E/ADN4697E
Rev. B | Page 5 of 20
Table 4. Test Voltages for Type 2 Receiver
Applied Voltages Input Voltage, Differential Input Voltage, Common Mode Receiver Output
V
A
(V) V
B
(V) V
ID
(V) V
IC
(V) RO (V)
+2.4 0 +2.4 +1.2 H
0 +2.4 −2.4 +1.2 L
+3.8 +3.65 +0.15 +3.725 H
+3.8 +3.75 +0.05 +3.775 L
−1.25 −1.4 +0.15 −1.325 H
−1.35 −1.4 +0.05 −1.375 L
TIMING SPECIFICATIONS
V
CC
= 3.0 V to 3.6 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 5.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 200 Mbps
PLH
PHL
Differential Output Rise/Fall Time t
R
, t
F
1 1.6 ns See Figure 24, Figure 27
Pulse Skew |t
PHL
– t
PLH
| t
SK
0 100 ps See Figure 24, Figure 27
Part-to-Part Skew
2
t
SK(PP)
1 ns See Figure 24, Figure 27
Period Jitter, RMS (1 Standard Deviation)
3
t
J(PER)
2 3 ps 100 MHz clock input
4
(see Figure 26)
Peak-to-Peak Jitter
3, 5
t
J(PP)
30 130 ps 200 Mbps 2
15
− 1 PRBS input
6
(see Figure 29)
Disable Time from High Level t
PHZ
7 ns See Figure 25, Figure 28
Disable Time from Low Level t
PLZ
7 ns See Figure 25, Figure 28
Enable Time to High Level t
PZH
7 ns See Figure 25, Figure 28
Enable Time to Low Level t
PZL
7 ns See Figure 25, Figure 28
RECEIVER
Propagation Delay t
RPLH
, t
RPHL
2 4 6 ns C
L
= 15 pF (see Figure 30, Figure 33)
Rise/Fall Time t
R
, t
F
1 2.3 ns C
L
= 15 pF (see Figure 30, Figure 33)
Pulse Skew |t
RPHL
– t
RPLH
| t
SK
C
L
= 15 pF (see Figure 30, Figure 33)
Type 1 Receiver (ADN4691E, ADN4693E)
Type 2 Receiver (ADN4696E, ADN4697E) 300 500 ps
Part-to-Part Skew
2
t
SK(PP)
1 ns C
L
= 15 pF (see Figure 30, Figure 33)
Period Jitter, RMS (1 Standard Deviation)
3
t
J(PER)
4 7 ps 100 MHz clock input
7
(see Figure 32)
Peak-to-Peak Jitter
3, 5
t
J(PP)
200 Mbps 2
15
− 1 PRBS input
8
(see Figure 35)
Type 1 Receiver (ADN4691E, ADN4693E) t
J(PP)
300 700 ps
Type 2 Receiver (ADN4696E, ADN4697E) 450 800 ps
Disable Time from High Level t
RPHZ
10 ns See Figure 31, Figure 34
Disable Time from Low Level t
RPLZ
10 ns See Figure 31, Figure 34
Enable Time to High Level t
RPZH
15 ns See Figure 31, Figure 34
Enable Time to Low Level t
RPZL
15 ns See Figure 31, Figure 34
1
All typical values are given for V
CC
= 3.3 V and T
A
= 25°C.
2
t
SK(PP)
is defined as the difference between the propagation delays of two devices between any specified terminals. This specification applies to devices at the same V
CC
and temperature, and with identical packages and test circuits.
3
Jitter parameters are guaranteed by design and characterization. Values do not include stimulus jitter.
4
t
R
= t
F
= 0.5 ns (10% to 90%), measured over 30,000 samples.
5
Peak-to-peak jitter specifications include jitter due to pulse skew (t
SK
).
6
t
R
= t
F
= 0.5 ns (10% to 90%), measured over 100,000 samples.
7
|V
ID
| = 400 mV (ADN4696E, ADN4697E), V
IC
= 1.1 V, t
R
= t
F
= 0.5 ns (10% to 90%), measured over 30,000 samples.
8
|V
ID
| = 400 mV (ADN4696E, ADN4697E), V
IC
= 1.1 V, t
R
= t
F
= 0.5 ns (10% to 90%), measured over 100,000 samples.
