AD5601/AD5611/AD5621 Data Sheet
Rev. H | Page 4 of 21
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
POWER REQUIREMENTS
V
DD
2.7 5.5 2.7 5.5 V All digital inputs at 0 V or V
DD
I
DD
for Normal Mode
DAC active and excluding load
current
V
DD
= ±4.5 V to ±5.5 V 75 100 75 100 μA V
IH
= V
DD
and V
IL
= GND
V
DD
= ±2.7 V to ±3.6 V 60 90 60 90 μA V
IH
= V
DD
and V
IL
= GND
I
DD
for All Power-Down Modes V
IH
= V
DD
and V
IL
= GND
V
DD
= ±4.5 V to ±5.5 V 0.5 0.5 μA V
IH
= V
DD
and V
IL
= GND
V
DD
= ±2.7 V to ±3.6 V 0.2 0.2 μA V
IH
= V
DD
and V
IL
= GND
POWER EFFICIENCY
I
OUT
/I
DD
96 96 % I
LOAD
= 2 mA and V
DD
= ±5 V
1
Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252.
2
Guaranteed by design and characterization, not production tested.
3
Total current flowing into all pins.
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted. See Figure 2.
Table 3.
Parameter Limit
1
Unit Test Conditions/Comments
t
1
2
33 ns min SCLK cycle time
t
2
5 ns min SCLK high time
t
3
5 ns min SCLK low time
t
4
10 ns min
SYNC
to SCLK falling edge setup time
t
5
5 ns min Data setup time
t
6
4.5 ns min Data hold time
t
7
0 ns min
SCLK falling edge to SYNC
rising edge
t
8
20 ns min
Minimum SYNC
high time
t
9
13 ns min
SYNC
rising edge to next SCLK falling edge ignored
1
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Maximum SCLK frequency is 30 MHz.
Figure 2. Timing Diagram
t
4
t
3
t
2
t
5
t
7
t
6
D0D1D2D14D15
SYNC
SCLK
06853-002
t
9
t
1
t
8
D15 D14
SDIN
