MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
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values originally held on C2a and C2b. These values
are then presented to the first stage quantizers and iso-
late the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the MAX1192
to track and sample/hold analog inputs of high frequen-
cies (>Nyquist). Both ADC inputs (INA+, INB+, INA-,
and INB-) can be driven either differentially or single
ended. Match the impedance of INA+ and INA-, as well
as INB+ and INB-, and set the common-mode voltage
to midsupply (V
DD
/2) for optimum performance.
Analog Inputs and Reference
Configurations
The MAX1192 full-scale analog input range is ±V
REF
with a common-mode input range of V
DD
/2 ±0.2V. V
REF
is the difference between V
REFP
and V
REFN
. The
MAX1192 provides three modes of reference operation.
The voltage at REFIN (V
REFIN
) sets the reference oper-
ation mode (Table 1).
In internal reference mode, connect REFIN to V
DD
or
leave REFIN unconnected. V
REF
is internally generated
to be 0.512V ±3%. COM, REFP, and REFN are low-
impedance outputs with V
COM
= V
DD
/2, V
REFP
= V
DD
/2
+ V
REF
/2, and V
REFN
= V
DD
/2 - V
REF
/2. Bypass REFP,
REFN, and COM each with a 0.33µF capacitor.
In buffered external reference mode, apply a 1.024V
±10% at REFIN. In this mode, COM, REFP, and REFN
are low-impedance outputs with V
COM
= V
DD
/2, V
REFP
=
V
DD
/2 + V
REFIN
/4, and V
REFN
= V
DD
/2 - V
REFIN
/4.
Bypass REFP, REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
In unbuffered external reference mode, connect REFIN
to GND. This deactivates the on-chip reference buffers
for COM, REFP, and REFN. With their buffers shut
down, these nodes become high-impedance inputs
(Figure 4) and can be driven through separate, external
reference sources. Drive V
COM
to V
DD
/2 ±10%, drive
V
REFP
to (V
DD
/2 +0.256V) ±10%, and drive V
REFN
to
(V
DD
/2 - 0.256V) ±10%. Bypass REFP, REFN, and COM
each with a 0.33µF capacitor.
For detailed circuit suggestions and how to drive this
dual ADC in buffered/unbuffered external reference
mode, see the
Applications Information
section.
Clock Input (CLK)
CLK accepts a CMOS-compatible signal level. Since
the interstage conversion of the device depends on the
repeatability of the rising and falling edges of the exter-
nal clock, use a clock with low jitter and fast rise and
fall times (<2ns). In particular, sampling occurs on the
rising edge of the clock signal, requiring this edge to
Figure 4. Unbuffered External Reference Mode Impedance
V
REFIN
REFERENCE MODE
>0.8 x V
DD
Internal reference mode. V
REF
is internally generated to be 0.512V. Bypass REFP, REFN, and COM
each with a 0.33µF capacitor.
1.024V ±10%
Buffered external reference mode. An external 1.024V ±10% reference voltage is applied to
REFIN. V
REF
is internally generated to be V
REFIN
/2. Bypass REFP, REFN, and COM each with a
0.33µF capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
<0.3V
Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference
sources. V
REF
is the difference between the externally applied V
REFP
and V
REFN
. Bypass REFP,
REFN, and COM each with a 0.33µF capacitor.
