SYMBOL
MAX
UNITS
I
SINK
0.256
-0.256
V
COM
V
DD
/ 2
V
REF
0.512
R
REFP
R
REFN
OV
DD
OV
DD
V
HYST
DC
IN
DIGITAL OUTPUTS (D7–D0, A/B)
OV
DD
OV
DD
I
LEAK
C
OUT
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.0V, OV
DD
= 1.8V, V
REFIN
= V
DD
(internal reference), C
L
10pF at digital outputs, f
CLK
= 22MHz, C
REFP
= C
REFN
= C
COM
=
0.33µF, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
MAX1192
PARAMETER
SYMBOL
CONDITIONS MIN TYP
MAX UNITS
POWER REQUIREMENTS
Analog Supply Voltage V
DD
2.7 3.0 3.6 V
Digital Output Supply Voltage
OV
DD
1.8 V
DD
V
Normal operating mode, f
IN
= 1.875MHz
at -0.5dB FS, f
CLK
= 7.5MHz,
CLK input from GND to V
DD
4.2 5.0
Normal operating mode, f
IN
= 5.5MHz
at -0.5dB FS, f
CLK
= 22MHz,
CLK input from GND to V
DD
9.1 10.5
Idle mode (tri-state), f
IN
= 1.875MHz at -
0.5dB FS, f
CLK
= 7.5MHz, CLK input from
GND to V
DD
4.2
Idle mode (tri-state), f
IN
= 5.5MHz at
-0.5dB FS, f
CLK
= 22MHz, CLK input from
GND to V
DD
9.1
Standby mode, f
CLK
= 7.5MHz, CLK input
from GND to V
DD
2.3
Standby mode, f
CLK
= 22MHz, CLK input
from GND to V
DD
4.9
mA
Analog Supply Current I
DD
Shutdown mode, CLK = GND or V
DD
,
PD0 = PD1 = OGND
0.6 5.0 µA
Normal operating mode,
f
IN
= 1.875MHz at -0.5dB FS,
f
CLK
= 7.5MHz, C
L
10pF
1.0
Normal operating mode,
f
IN
= 5.5MHz at -0.5dB FS,
f
CLK
= 22MHz, C
L
10pF
2.9
mA
Idle mode (tri-state), DC input,
CLK = GND or V
DD,
PD0 = OV
DD
, PD1 = OGND
0.1 5.0
Standby mode, DC input, CLK = GND or
V
DD,
PD0 = OGND, PD1 = OV
DD
0.1
Digital Output Supply Current
(Note 3)
I
ODD
Shutdown mode, CLK = GND or V
DD
,
PD0 = PD1 = OGND
0.1 5.0
µA
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.0V, OV
DD
= 1.8V, V
REFIN
= V
DD
(internal reference), C
L
10pF at digital outputs, f
CLK
= 22MHz, C
REFP
= C
REFN
= C
COM
=
0.33µF, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
_______________________________________________________________________________________ 5
MAX1192
Ultra-Low-Power, 22Msps, Dual 8-Bit ADC
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3.0V, OV
DD
= 1.8V, V
REFIN
= V
DD
(internal reference), C
L
10pF at digital outputs, f
CLK
= 22MHz, C
REFP
= C
REFN
= C
COM
=
0.33µF, T
A
= -40°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.) (Note 1)
Note 1: Specifications +25°C guaranteed by production test, <+25°C guaranteed by design and characterization.
Note 2: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dB FS referenced to the
amplitude of the digital output. SNR and THD are calculated using HD2 through HD6.
Note 3: The power consumption of the output driver is proportional to the load capacitance (C
L
).
Note 4: Guaranteed by design and characterization. Not production tested.
Note 5: SINAD settles to within 0.5dB of its typical value.
Note 6: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the
second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tone bins.
Note 7: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
PARAMETER
SYMBOL
CONDITIONS MIN TYP
MAX
UNITS
TIMING CHARACTERISTICS
CLK Rise to CHA Output Data
Valid
t
DOA
50% of C LK to 50% of d ata,
Fi g ur e 5 ( N ote 4)
1 6 8.5 ns
CLK Fall to CHB Output Data
Valid
t
DOB
50% of C LK to 50% of d ata,
Fi g ur e 5 ( N ote 4)
1 6 8.5 ns
CLK Rise/Fall to A/B Rise/Fall
Time
t
DA/B
50% of C LK to 50% of A/B,
Fi g ur e 5 ( N ote 4)
1 6 8.5 ns
PD1 Rise to Output Enable t
EN
PD0 = OV
DD
5ns
PD1 Fall to Output Disable t
DIS
PD0 = OV
DD
5ns
CLK Duty Cycle 50 %
CLK Duty Cycle Variation ±10 %
Wake-Up Time from Shutdown
Mode
t
WAKE
,
SD
(Note 5) 20 µs
Wake-Up Time from Standby
Mode
t
WAKE
,
ST
(Note 5) 5.4 µs
Digital Output Rise/Fall Time 20% to 80% 2 ns
INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
f
IN,X
= 5.5MHz at -0.5dB FS,
f
IN,Y
= 0.3MHz at -0.5dB FS (Note 6)
-75 dB
Amplitude Matching f
IN
= 5.5MHz at -0.5dB FS (Note 7)
±0.03
dB
Phase Matching f
IN
= 5.5MHz at -0.5dB FS (Note 7) ±0.1
Degrees

MAX1192ETI+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 8-Bit 2Ch 22Msps 3.6V Precision ADC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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