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MAX1876EEG+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
MAX1875/MAX1876
High-Side Gate-Drive Supply (BST_)
Gate-drive voltages for the high-side N-channel switch-
es are generated by the flying-capacitor boost circuits
(Figure 3). A boost capacitor (connected from BST_ to
LX_) provides power to the high-side MOSFET driver.
On startup, the synchronous rectifier (low-side MOSFET)
forces LX_ to ground and charges the boost capacitor to
5V. On the second half-cycle, after the low-side MOSFET
turns off, the high-side MOSFET is turned on by closing
an internal switch between BST_ and DH_. This provides
the necessary gate-to-source voltage to turn on the high-
side switch, an action that boosts the 5V gate-drive
signal above V
IN
. The current required to drive the high-
side MOSFET gates (f
SWITCH
✕
Q
G
) is ultimately drawn
from V
L
.
MOSFET Gate Drivers (DH_, DL_)
The DH and DL drivers are optimized for driving moder-
ate-size N-channel high-side and larger low-side power
MOSFETs. This is consistent with the low-duty factor
seen with large V
IN
- V
OUT
differential. The DL_ low-side
drive waveform is always the complement of the DH_
high-side drive waveform (with controlled dead time to
prevent cross-conduction or “shoot-through”). An adap-
tive dead-time circuit monitors the DL_ output and pre-
vents the high-side FET from turning on until DL_ is fully
off. There must be a low-resistance, low-inductance
path from the DL_ driver to the MOSFET gate in order
for the adaptive dead-time circuit to work properly.
Otherwise, the sense circuitry in the MAX1875/MAX1876
interprets the MOSFET gate as “off” while there is actu-
ally charge still left on the gate. Use very short, wide
traces (50mils to 100mils wide if the MOSFET is 1in from
the device). The dead time at the DH-off edge is deter-
mined by a fixed 30ns internal delay.
Synchronous rectification reduces conduction losses in
the rectifier by replacing the normal low-side Schottky
catch diode with a low-resistance MOSFET switch.
Additionally, the MAX1875/MAX1876 uses the synchro-
nous rectifier to ensure proper startup of the boost gate-
driver circuit and to provide the current-limit signal.
The internal pulldown transistor that drives DL_ low is
robust, with a 0.5Ω (typ) on-resistance. This low on-
resistance helps prevent DL_ from being pulled up dur-
ing the fast rise-time of the LX_ node, due to capacitive
coupling from the drain to the gate of the low-side syn-
chronous-rectifier MOSFET. However, for high-current
applications, some combinations of high- and low-side
FETs can cause excessive gate-drain coupling, leading
to poor efficiency, EMI, and shoot-through currents.
This can be remedied by adding a resistor (typically
less than 5Ω) in series with BST_, which increases the
turn-on time of the high-side FET without degrading the
turn-off time (Figure 3).
Current-Limit Circuit (ILIM_)
The current-limit circuit employs a “valley” current-sens-
ing algorithm that uses the on-resistance of the low-side
MOSFET as a current-sensing element. If the current-
sense signal is above the current-limit threshold, the
MAX1875/MAX1876 does not initiate a new cycle
(Figure 4). Since valley current sensing is employed, the
actual peak current is greater than the current-limit
threshold by an amount equal to the inductor ripple cur-
rent. Therefore, the exact current-limit characteristic and
maximum load capability are a function of the low-side
MOSFET’s on-resistance, current-limit threshold, induc-
tor value, and input voltage. The reward for this uncer-
tainty is robust, lossless overcurrent sensing that does
not require costly sense resistors.
The adjustable current limit accommodates MOSFETs
with a wide range of on-resistance characteristics (see
the Design Procedure section). The current-limit thresh-
old is adjusted with an external resistor at ILIM_ (Figure
1). The adjustment range is from 50mV to 300mV, cor-
responding to resistor values of 100kΩ to 600kΩ. In
adjustable mode, the current-limit threshold across the
low-side MOSFET is precisely 1/10th the voltage seen
at ILIM_. However, the current-limit threshold defaults
to 100mV when ILIM is tied to V
L
. The logic threshold
for switchover to this 100mV default value is approxi-
mately V
L
- 0.5V.
Adjustable foldback current limit reduces power dissi-
pation during short-circuit conditions (see the Design
Procedure section).
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors do not corrupt the cur-
rent-sense signals seen by LX_ and PGND. The IC
must be mounted close to the low-side MOSFET with
short, direct traces making a Kelvin sense connection
so that trace resistance does not add to the intended
sense resistance of the low-side MOSFET.
Undervoltage Lockout and Startup
If V
L
drops below 4.5V, the MAX1875/MAX1876 assumes
that the supply and reference voltages are too low to
make valid decisions and activates the undervoltage lock-
out (UVLO) circuitry which forces DL and DH low to inhibit
switching. RST is also forced low during UVLO. After V
L
rises above 4.5V, the controller powers up the outputs.
Enable (EN), Soft-Start, and Soft-Stop
Pull EN high to enable or low to shutdown both regula-
tors. During shutdown the supply current drops to 1mA
(max), LX enters a high-impedance state (DH_ con-
nected to LX_, and DL_ connected to PGND), and
COMP_ is discharged to GND through a 17Ω resistor.
V
L
and REF remain active in shutdown. For “always-on”
operation, connect EN to V
L
.
Dual 180° Out-of-Phase PWM Step-
Down Controllers with POR
10 ______________________________________________________________________________________
On the rising edge of EN both controllers enter soft-
start. Soft-start gradually ramps up to the reference
voltage seen by the error amplifier in order to control
the outputs’ rate of rise and reduce input surge cur-
rents during startup. The soft-start period is 1024 clock
cycles (1024/f
SW
), and the internal soft-start DAC
ramps up the voltage in 64 steps. The output reaches
regulation when soft-start is completed. On the falling
edge of EN both controllers simultaneously enter soft-
stop, which reverses the soft-start ramp. The part
enters shutdown after soft-stop is complete.
Reset Output (MAX1876 Only)
RST is an open-drain output. RST pulls low when either
output falls below 90% of its nominal regulation voltage.
Once both outputs exceed 90% of their nominal regulation
voltages and both soft-start cycles are completed, RST
goes high impedance. To obtain a logic-voltage output,
connect a pullup resistor from RST to the logic supply volt-
age. A 100kΩ resistor works well for most applications. If
unused, leave RST grounded or unconnected.
Clock Synchronization (SYNC, CKO)
SYNC serves two functions: SYNC selects the clock
output (CKO) type used to synchronize slave con-
trollers, or it serves as a clock input so the
MAX1875/MAX1876 can be synchronized with an exter-
nal clock signal. This allows the MAX1875/MAX1876 to
funtion as either a master or slave. CKO provides a
clock signal synchronized to the MAX1875/MAX1876s’
switching frequency, allowing either in-phase (SYNC =
GND) or 90° out-of-phase (SYNC = V
L
) synchronization
of additional DC-DC controllers (Figure 5). The
MAX1875/MAX1876 support the following three operat-
ing modes:
• SYNC = GND: The CKO output frequency equals
REG1’s switching frequency (f
CKO
= f
DH1
) and the
CKO signal is in phase with REG1’s switching fre-
quency. This provides 2-phase operation when syn-
chronized with a second slave controller.
• SYNC = VL: The CKO output frequency equals two
times REG1’s switching frequency (f
CKO
= 2f
DH1
)
and the CKO signal is phase shifted by 90° with
respect to REG1’s switching frequency. This pro-
vides 4-phase operation when synchronized with a
second MAX1875/MAX1876 (slave controller).
• SYNC Driven by External Oscillator: The controller
generates the clock signal by dividing down the
SYNC input signal, so that the switching frequency
equals half the synchronization frequency (f
SW
=
f
SYNC
/2). REG1’s conversion cycles initiate on the ris-
ing edge of the internal clock signal. The CKO output
frequency and phase match REG1’s switching fre-
quency (f
CKO
= f
DH1
) and the CKO signal is in
phase. Note that the MAX1875/MAX1876 still require
R
OSC
when SYNC is externally clocked and the inter-
nal oscillator frequency should be set to 50% of the
synchronization frequency (f
OSC
= 0.5 f
SYNC
).
Thermal Overload Protection
Thermal overload protection limits total power dissipation
in the MAX1875/MAX1876. When the device’s die-junc-
tion temperature exceeds T
J
= +160°C, an on-chip ther-
mal sensor shuts down the device, forcing DL_ and DH_
low, allowing the IC to cool. The thermal sensor turns the
part on again after the junction temperature cools by
10°C. During thermal shutdown, the regulators shut
down, RST goes low, and soft-start is reset. If the V
L
lin-
ear-regulator output is short-circuited, thermal-overload
protection is triggered.
Design Procedure
Effective Input Voltage Range
Although, the MAX1875/MAX1876 controllers can oper-
ate from input supplies ranging from 4.75V to 23V, the
input voltage range can be effectively limited by the
MAX1875/MAX1876s’ duty-cycle limitations. The maxi-
mum input voltage is limited by the minimum on-time
(t
ON(MIN)
):
V
V
tf
IN MAX
OUT
ON MIN SW
()
()
≤
MAX1875/MAX1876
Dual 180° Out-of-Phase PWM Step-
Down Controllers with POR
______________________________________________________________________________________ 11
V
L
BST_
DH_
LX_
5Ω
INPUT
(V
IN
)
MAX1875
Figure 3. Reducing the Switching-Node Rise Time
MAX1875/MAX1876
where t
ON(MIN)
is 100ns. The minimum input voltage is
limited by the switching frequency and minimum off-
time, which determine the maximum duty cycle
(D
MAX
= 1 - f
SW
t
OFF(MIN)
):
where V
DROP1
is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances. V
DROP2
is
the sum of the resistances in the charging path, includ-
ing high-side switch, inductor, and PC board resis-
tances.
Setting the Output Voltage
For 1V or greater output voltages, set the MAX1875/
MAX1876 output voltage by connecting a voltage-
divider from the output to FB_ to GND (Figure 6). Select
R_B (FB_ to GND resistor) to between 1kΩ and 10kΩ.
Calculate R_A (OUT_ to FB_ resistor) with the following
equation:
where V
SET
= 1V (see the Electrical Characteristics)
and V
OUT
can range from V
SET
to 18V.
For output voltages below 1V, set the MAX1875/
MAX1876 output voltage by connecting a voltage-
divider from the output to FB_ to REF (Figure 6). Select
R_C (FB to REF resistor) in the 1kΩ to 10kΩ range.
Calculate R_A with the following equation:
where V
SET
= 1V, V
REF
= 2V (see the Electrical
Characteristics), and V
OUT
can range from 0 to V
SET
.
RA RC
VV
VV
SET OUT
REF SET
__=
-
-
RA RB
V
V
OUT
SET
__=
-1
V
VV
ft
VV
IN MIN
OUT DROP
SW OFF MIN
DROP DROP()
()
=
+
+
1
21
1-
-
Dual 180° Out-of-Phase PWM Step-
Down Controllers with POR
12 ______________________________________________________________________________________
INDUCTOR CURRENT
I
LIMIT
I
LOAD
0 TIME
-I
PEAK
Figure 4. “Valley” Current-Limit Threshold Point
SYNC
SLAVE
OSC
SYNC
CK0
MASTER
V
L
4-PHASE SYSTEM2-PHASE SYSTEM
DH1
DH2
DH1
DH2
MASTER
SLAVE
180° PHASE SHIFT 90° PHASE SHIFT
DH1
DH2
DH1
DH2
MASTER
SLAVE
MAX1875
SYNC
SLAVE
OSC OSC
SYNC
CK0
MASTER
V
L
MAX1875 MAX1875
Figure 5. Synchronized Controllers
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

MAX1876EEG+

Mfr. #:
Buy MAX1876EEG+
Manufacturer:
Maxim Integrated
Description:
Switching Controllers Dual 180 Out PWM Step-Down
Lifecycle:
New from this manufacturer.
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