MAX1875/MAX1876
the switching frequency and minimum off-time specifi-
cations. This error is more significant at higher frequen-
cies. Also, keep in mind that transient response
performance of buck regulators operated close to
dropout is poor, and bulk output capacitance must
often be added (see the V
SAG
equation in the Design
Procedure section).
The absolute point of dropout is when the inductor cur-
rent ramps down during the minimum off-time (∆I
DOWN
)
as much as it ramps up during the maximum on-time
(∆I
UP
). The ratio h = ∆I
UP
/∆I
DOWN
is an indicator of the
ability to slew the inductor current higher in response to
increased load, and must always be greater than 1. As
h approaches 1, the absolute minimum dropout point,
the inductor current cannot increase as much during
each switching cycle and V
SAG
greatly increases
unless additional output capacitance is used.
A reasonable minimum value for h is 1.5, but adjusting
this up or down allows tradeoffs between V
SAG
, output
capacitance, and minimum operating voltage. For a
given value of h, the minimum operating voltage can be
calculated as:
where V
DROP1
is the sum of the parasitic voltage drops
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; V
DROP2
is
the sum of the resistances in the charging path, includ-
ing high-side switch, inductor, and PC board resis-
tances; and t
OFF(MIN)
is from the Electrical
Characteristics. The absolute minimum input voltage is
calculated with h = 1.
If the calculated V+
(MIN)
is greater than the required
minimum input voltage, then reduce the operating fre-
quency or add output capacitance to obtain an accept-
able V
SAG
. If operation near dropout is anticipated,
calculate V
SAG
to be sure of adequate transient
response.
Dropout Design Example:
V
OUT
= 5V
f
SW
= 600kHz
t
OFF(MIN)
= 250ns
V
DROP1
= V
DROP2
= 100mV
h = 1.5
Calculating again with h = 1 gives the absolute limit of
dropout:
Therefore, V
IN
must be greater than 6V, even with very
large output capacitance, and a practical input voltage
with reasonable output capacitance would be 6.58V.
Improving Noise Immunity
Applications where the MAX1875/MAX1876 must oper-
ate in noisy environments can typically adjust their con-
troller’s compensation to improve the system’s noise
immunity. In particular, high-frequency noise coupled
into the feedback loop causes jittery duty cycles. One
solution is to lower the crossover frequency (see the
Compensation section).
PC Board Layout Guidelines
Careful PC board layout is critical to achieve low
switching losses and clean, stable operation. This is
especially true for dual converters where one channel
can affect the other. Refer to the MAX1875/MAX1876
EV kit data sheet for a specific layout example.
If possible, mount all of the power components on the
top side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
• Isolate the power components on the top side from
the analog components on the bottom side with a
ground shield. Use a separate PGND plane under
the OUT1 and OUT2 sides (referred to as PGND1
and PGND2). Avoid the introduction of AC currents
into the PGND1 and PGND2 ground planes. Run the
power plane ground currents on the top side only.
• Use a star ground connection on the power plane to
minimize the crosstalk between OUT1 and OUT2.
• Keep the high-current paths short, especially at the
ground terminals. This practice is essential for sta-
ble, jitter-free operation.
• Connect GND and PGND together close to the IC.
Do not connect them together anywhere else.
Carefully follow the grounding instructions under
step 4 of the Layout Procedure section.
