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LT3759HMSE#PBF

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LT3759
10
3759fc
For more information www.linear.com/3759
regulates the INTV
CC
to 3.75V. V
IN
LDO is turned off when
the INTV
CC
voltage is greater than 3.75V (typical). Both
LDO’s can be turned off if the INTV
CC
pin is driven by a
supply of 4.75V or higher but less than 8V (the INTV
CC
maximum voltage rating is 8V). A table of the LDO sup-
ply and output voltage combination is shown in Table 1.
Table 1. LDO’s Supply and Output Voltage Combination (Assuming
That the LDO Dropout Voltage is 0.15V)
SUPPLY VOLTAGES LDO OUTPUT
LDO STATUS
(Note 7)
V
IN
DRIVE INTV
CC
V
IN
≤ 3.9V V
DRIVE
< V
IN
V
IN
– 0.15V #1 Is ON
V
DRIVE
= V
IN
V
IN
– 0.15V #1 #2 are ON
V
IN
< V
DRIVE
< 4.9V V
DRIVE
– 0.15V #2 Is ON
4.9V ≤ V
DRIVE
≤ 42V 4.75V #2 Is ON
3.9V < V
IN
≤ 42V V
DRIVE
< 3.9V 3.75V #1 Is ON
V
DRIVE
= 3.9V 3.75V #1 #2 are ON
3.9V < V
DRIVE
< 4.9V V
DRIVE
– 0.15V #2 Is ON
4.9V ≤ V
DRIVE
≤ 42V 4.75V #2 Is ON
Note 7: #1 is V
IN
LDO and #2 is DRIVE LDO
The DRIVE pin provides flexibility to power the gate driver
and the internal loads from a supply that is available only
when the switcher is enabled and running. If not used, the
DRIVE pin should be tied to V
IN
.
The INTV
CC
pin must be bypassed to ground immediately
adjacent to the INTV
CC
pin with a minimum of 4.7µF ceramic
capacitor. Good bypassing is necessary to supply the high
transient currents required by the MOSFET gate driver.
If a low input voltage operation is expected (V
IN
is 3V or
less), low threshold MOSFETs should be used. The LT3759
contains an undervoltage lockout comparator A8 for the
internal INTV
CC
supply. The INTV
CC
undervoltage (UV)
threshold is 1.3V (typical), with 100mV hysteresis, to
ensure that the MOSFETs have sufficient gate drive voltage
before turning on. The logic circuitry within the LT3759
is also powered from the internal INTV
CC
supply. When
INTV
CC
is below the UV threshold, the GATE pin will be
forced to GND and the soft-start operation will be triggered.
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
The on-chip power dissipation can be a significant con-
cern when a large power MOSFET is being driven at a
high frequency and the V
IN
voltage is high. It is important
to limit the power dissipation with proper selection of a
MOSFET and/or an operating frequency so the LT3759
does not exceed its maximum junction temperature rating.
The junction temperature T
J
can be estimated using the
following equations:
T
J
= T
A
+P
IC
• θ
JA
T
A
= ambient temperature
θ
JA
= junction-to-ambient thermal resistance
P
IC
= IC power consumption = V
IN
• (I
Q
+ I
DRIVE
)
(Assume the DRIVE pin is connected to V
IN
Supply)
I
Q
= V
IN
operation I
Q
= 1.8mA
I
DRIVE
= average gate drive current = f • Q
G
f = switching frequency
Q
G
= power MOSFET total gate charge
The LT3759 uses packages with an exposed pad for en-
hanced thermal conduction. With proper soldering to the
exposed pad on the underside of the package and a full
copper plane underneath the device, thermal resistance
(θ
JA
) will be about 40°C/W for the MSE package.
The LT3759 has an internal INTV
CC
I
DRIVE
current limit
function to protect the IC from excessive on-chip power
dissipation. If I
DRIVE
reaches the current limit, INTV
CC
voltage will fall and may trigger the soft-start.
There is a trade-off between the operating frequency and
the size of the power MOSFET (Q
G
) in order to maintain
a reliable IC junction temperature. Prior to lowering the
operating frequency, however, be sure to check with
power MOSFET manufacturers for their most recent low
Q
G
, low R
DS(ON)
devices. Power MOSFET manufacturing
technologies are continually improving, with newer and
better performance devices being introduced almost yearly.
Operating Frequency and Synchronization
The choice of operating frequency may be determined
by on-chip power dissipation, otherwise it is a trade-off
between efficiency and component size. Low frequency
APPLICATIONS INFORMATION
LT3759
11
3759fc
For more information www.linear.com/3759
operation improves efficiency by reducing gate drive cur-
rent and MOSFET and diode switching losses. However,
lower frequency operation requires a physically larger loop
inductor. Switching frequency also has implications for
loop compensation. The LT3759 uses a constant-frequency
architecture that can be programmed over a 100kHz to
1MHz range with a single external resistor from the RT pin
to ground, as shown in Figure 1. The RT pin must have
an external resistor to GND for proper operation of the
LT3759. A table for selecting the value of R
T
for a given
operating frequency is shown in Table 2.
Table 2. Timing Resistor (R
T
) Value
OSCILLATOR FREQUENCY (kHz) R
T
(kΩ)
100 86.6
200 41.2
300 27.4
400 21.0
500 16.5
600 13.7
700 11.5
800 9.76
900 8.45
1000 6.81
The switching frequency of the LT3759 can be synchronized
to the positive edge of an external clock source. By provid-
ing a digital clock signal into the SYNC pin, the LT3759 will
operate at the SYNC clock frequency. If this feature is used,
an R
T
resistor should be chosen to program a switching
frequency 20% slower than SYNC pulse frequency. The
SYNC pulse should have a minimum pulse width of 200ns.
Tie the SYNC pin to GND if this feature is not used.
Duty Cycle Consideration
Switching duty cycle is a key variable defining converter
operation. As such, its limits must be considered. Minimum
on-time is the smallest time duration that the LT3759 is
capable of turning on the power MOSFET. This time is
generally about 170ns (typical) (see Minimum On-Time
in the Electrical Characteristics table). In each switching
cycle, the LT3759 keeps the power switch off for at least
170ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).
The minimum on-time and minimum off-time and the
switching frequency define the minimum and maximum
switching duty cycles a converter is able to generate:
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
Programming the Output Voltage
The output voltage (V
OUT
) is set by a resistor divider, as
shown in Figure 1. The positive V
OUT
and negative V
OUT
are set by the following equations:
V
OUT(POSITIVE)
= 1.6V • 1+
R2
R1
V
OUT(NEGATIVE)
= –0.8V • 1+
R2
R1
The resistors R1 and R2 are typically chosen so that the
error caused by the current flowing into the FBX pin dur-
ing normal operation is less than 1% (this translates to a
maximum value of R1 at about 158k).
Soft-Start
The LT3759 contains several features to limit peak switch
currents and output voltage (V
OUT
) overshoot during
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since V
OUT
is far from its final value,
the feedback loop is saturated and the regulator tries to
charge the output capacitor as quickly as possible, resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
LT3759 addresses this mechanism with the SS pin. As
shown in Figure 1, the SS pin reduces the power MOSFET
current by pulling down the VC pin through Q2. In this
way the SS allows the output capacitor to charge gradually
toward its final value while limiting the start-up peak
currents.
APPLICATIONS INFORMATION
LT3759
12
3759fc
For more information www.linear.com/3759
Besides start-up, soft-start can also be triggered by
INTV
CC
undervoltage lockout and/or thermal lockout, which
causes the LT3759 to stop switching immediately. The SS
pin will be discharged by Q3. When all faults are cleared
and the SS pin has been discharged below 0.2V, a 10µA
current source I
S2
starts charging the SS pin, initiating a
soft-start operation.
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
T
SS
= C
SS
•
1.25V
10µA
FBX Frequency Foldback
When V
OUT
is very low during start-up or a short-circuit
fault on the output, the switching regulator must operate
at low duty cycles to maintain the power switch current
within the current limit range, since the inductor current
decay rate is very low during switch off time. The minimum
on-time limitation may prevent the switcher from attaining
a sufficiently low duty cycle at the programmed switch-
ing frequency. So, the switch current will keep increasing
through each switch cycle, exceeding the programmed
current limit. To prevent the switch peak currents from
exceeding the programmed value, the LT3759 contains
a frequency foldback function to reduce the switching
frequency when the FBX voltage is low (see the Normal-
ized Switching Frequency vs FBX graph in the Typical
Performance Characteristics section).
Some frequency foldback waveforms are shown in the
Typical Applications section. The frequency foldback func-
tion prevents I
L
from exceeding the programmed limits
because of the minimum on-time.
During frequency foldback, external clock synchronization
is disabled to allow the frequency reducing operation to
function properly.
Thermal Lockout
If the LT3759 die temperature reaches 165°C (typical),
the part will go into thermal lockout. The power switch
will be turned off. A soft-start operation will be triggered.
The part will be enabled again when the die temperature
has dropped by 5°C (nominal).
Loop Compensation
Loop compensation determines the stability and transient
performance. The LT3759 uses current mode control to
regulate the output which simplifies loop compensation.
The optimum values depend on the converter topology, the
component values and the operating conditions (including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3759, a series resistor-capacitor
network is usually connected from the VC pin to GND.
Figure 1 shows the typical VC compensation network. For
most applications, the capacitor should be in the range of
470pF to 22nF, and the resistor should be in the range of
5k to 50k. A small capacitor is often connected in paral-
lel with the RC compensation network to attenuate the
VC voltage ripple induced from the output voltage ripple
through the internal error amplifier. The parallel capacitor
usually ranges in value from 10pF to 100pF. A practical
approach to design the compensation network is to start
with one of the circuits in this data sheet that is similar
to your application, and tune the compensation network
to optimize the performance. Stability should then be
checked across all operating conditions, including load
current, input voltage and temperature.
SENSE Pin Programming
For control and protection, the LT3759 measures the
power MOSFET current by using a sense resistor (R
SENSE
)
between GND and the MOSFET source. Figure 2 shows a
typical wave-form of the sense voltage (V
SENSE
) across the
sense resistor. It is important to use Kelvin traces between
the SENSE pin and R
SENSE
, and to place the IC GND as
close as possible to the GND terminal of the R
SENSE
for
proper operation.
Figure 2. The Sense Voltage During a Switching Cycle
APPLICATIONS INFORMATION
3759 F02
V
SENSE(PEAK)
ΔV
SENSE
=
χ
• V
SENSE(MAX)
V
SENSE
t
DT
S
V
SENSE(MAX)
T
S
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LT3759HMSE#PBF

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Buy LT3759HMSE#PBF
Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators Boost, Flyback, SEPIC, and Inverting Controller
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