LT3759
23
3759fc
For more information www.linear.com/3759
Inverting Converter: Switch Duty Cycle and Frequency
For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
negative output voltage (V
OUT
) and the input voltage (V
IN
).
The maximum duty cycle (D
MAX
) occurs when the converter
has the minimum input voltage:
D
MAX
=
V
OUT
– V
D
V
OUT
– V
D
– V
IN(MIN)
Inverting Converter: Inductor, Sense Resistor, Power
MOSFET, Output Diode and Input Capacitor Selections
The selections of the inductor, sense resistor, power
MOSFET, output diode and input capacitor of an inverting
converter are similar to those of the SEPIC converter. Please
refer to the corresponding SEPIC converter sections.
Inverting Converter: Output Capacitor Selection
The inverting converter requires much smaller output
capacitors than those of the boost and SEPIC converters
for similar output ripples. This is due to the fact that, in
the inverting converter, the inductor L2 is in series with the
output, and the ripple current flowing through the output
capacitors are continuous. The output ripple voltage is
produced by the ripple current of L2 flowing through the
ESR and bulk capacitance of the output capacitor:
∆V
OUT(P−P)
= ∆I
L2
• ESR
COUT
+
1
8 • f
O SC
• C
OUT
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
I
RMS(COUT)
> 0.3 • DI
L2
Inverting Converter: Selecting the DC Coupling
Capacitor
The DC voltage rating of the DC coupling capacitor (C
DC
,
as shown in Figure 9) should be larger than the maximum
input voltage minus the output voltage (negative voltage):
CDC
IN(MAX)
OUT
C
DC
has nearly a rectangular current waveform. During
the switch off-time, the current through C
DC
is I
IN
, while
approximately –I
O
flows during the on-time. The RMS
rating of the coupling capacitor is determined by the fol-
lowing equation:
I
RMS(CDC)
>I
O(MAX)
•
D
MAX
1–D
MAX
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C
DC
.
Board Layout
The high speed operation of the LT3759 demands careful
attention to board layout and component placement. The
exposed pad of the package is the only GND terminal of
the IC, and is important for thermal management of the
IC. Therefore, it is crucial to achieve a good electrical and
thermal contact between the exposed pad and the ground
plane of the board. For the LT3759 to deliver its full output
power, it is imperative that a good thermal path be pro-
vided to dissipate the heat generated within the package.
It is recommended that multiple vias in the printed circuit
board be used to conduct heat away from the IC and into
a copper plane with as much area as possible.
To prevent radiation and high frequency resonance prob-
lems, proper layout of the components connected to the
IC is essential, especially the power paths with higher di/
dt. The following high di/dt loops of different topologies
should be kept as tight as possible to reduce inductive
ringing:
• In boost configuration, the high di/dt loop contains the
output capacitor, the sensing resistor, the power MOSFET
and the Schottky diode.
APPLICATIONS INFORMATION
