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PCA9557BSHP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30
PCA9557 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 10 December 2013 10 of 30
NXP Semiconductors
PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
8.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘master’ and the devices which are controlled by
the master are the ‘slaves’ (see Figure 12
).
8.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from
transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of
each byte. Also a master must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter. The device that acknowledges has to
pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold
times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Fig 11. Definition of START and STOP conditions
mba608
SDA
SCL
P
STOP condition
S
START condition
Fig 12. System configuration
002aaa966
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
I
2
C-BUS
MULTIPLEXER
SLAVE
PCA9557 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 10 December 2013 11 of 30
NXP Semiconductors
PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
8.4 Bus transactions
Data is transmitted to the PCA9557 registers using Write Byte transfers (see Figure 14
and Figure 15
). Data is read from the PCA9557 registers using Read and Receive Byte
transfers (see Figure 16
and Figure 17).
Fig 13. Acknowledgement on the I
2
C-bus
002aaa987
S
START
condition
9821
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from master
Fig 14. Write to output port register
0 AS
slave address
START condition R/W acknowledge
from slave
002aad281
00000010
command byte
A
acknowledge
from slave
12345678SCL 9
SDA
DATA 1 A
write to port
data out from port
t
v(Q)
acknowledge
from slave
DATA 1 VALID
data to port
0 1 1 A2 A1 A00
P
STOP
condition
Fig 15. Write to I/O configuration or polarity inversion registers
0 AS
slave address
START condition R/W acknowledge
from slave
002aad282
0000011/00
command byte
A
acknowledge
from slave
12345678SCL 9
SDA
DATA A
acknowledge
from slave
data to register
0 1 1 A2 A1 A00
P
STOP
condition
PCA9557 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 10 December 2013 12 of 30
NXP Semiconductors
PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
Fig 16. Read from register
0 1 1 A2 A1 A0 0 AS0
START condition R/W
acknowledge
from slave
002aad283
A
acknowledge
from slave
SDA
A P
acknowledge
from master
data from register
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
(cont.)
1 A
R/W
acknowledge
from slave
slave address
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
NA
no acknowledge
from master
data from register
DATA (last byte)
command byte
0 1 1 A2 A1 A00
Remark: This figure assumes the command byte has previously been programmed with 00h.
Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge
phase is valid (output mode). Input data is lost.
Fig 17. Read input port register
0 1 1 A2 A1 A0 1 AS0
START condition R/W acknowledge
from slave
002aad284
A
acknowledge
from master
SDA NA
read from
port
data into
port
P
t
h(D)
data from port
no acknowledge
from master
data from port
DATA 4
slave address
DATA 1
STOP
condition
DATA 2 DATA 3 DATA 4
t
su(D)
DATA 1
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30

PCA9557BSHP

Mfr. #:
Buy PCA9557BSHP
Manufacturer:
NXP Semiconductors
Description:
Interface - I/O Expanders 8-bit I2C-bus and SMBus I/O port with reset
Lifecycle:
New from this manufacturer.
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