PCA9557BSHP Datasheet PCA9557D,118, PCA9557PW,118, PCA9557BS,118 | P7-P9

Product data sheet Rev. 7 — 10 December 2013 7 of 30

NXP Semiconductors

PCA9557

8-bit I

C-bus and SMBus I/O port with reset

7. Functional description

Refer to Figure 1 “Block diagram of PCA9557”.

7.1 Device address

Following a START condition the bus master must output the address of the slave it is

accessing. The address of the PCA9557 is shown in Figure 8

. To conserve power, no

internal pull-up resistors are incorporated on the hardware selectable address pins and

they must be pulled HIGH or LOW.

The last bit of the slave address defines the operation to be performed. When set to

logic 1 a read is selected, while a logic 0 selects a write operation.

7.2 Control register

Following the successful acknowledgement of the slave address, the bus master will send

a byte to the PCA9557, which will be stored in the control register. This register can be

written and read via the I

C-bus.

Fig 8. PCA9557 device address

002aad279

0 0 1 1 A2 A1 A0 R/W

fixed

slave address

programmable

Fig 9. Control register

Table 4. Register definition

D1 D0 Name Access Description

0 0 Register 0 read-only Input port register

0 1 Register 1 read/write Output port register

1 0 Register 2 read/write Polarity inversion register

1 1 Register 3 read/write Configuration register

002aad280

0 0 0 0 0 0 D1 D0

76543210bit:

Product data sheet Rev. 7 — 10 December 2013 8 of 30

NXP Semiconductors

PCA9557

8-bit I

C-bus and SMBus I/O port with reset

7.3 Register descriptions

7.3.1 Register 0 - Input port register

This register is a read-only port. It reflects the incoming logic levels of the pins, regardless

of whether the pin is defined as an input or an output by the Configuration register. Writes

to this register have no effect.

7.3.2 Register 1 - Output port register

This register reflects the outgoing logic levels of the pins defined as outputs by the

Configuration register. Bit values in this register have no effect on pins defined as inputs.

In turn, reads from this register reflect the value that is in the flip-flop controlling the output

selection, not the actual pin value.

7.3.3 Register 2 - Polarity inversion register

This register enables polarity inversion of pins defined as inputs by the Configuration

polarity is inverted. If a bit in this register is cleared (written with logic 0), the

corresponding port pin’s original polarity is retained.

7.3.4 Register 3 - Configuration register

This register configures the directions of the I/O pins. If a bit in this register is set, the

corresponding port pin is enabled as an input with high-impedance output driver. If a bit in

this register is cleared, the corresponding port pin is enabled as an output.

Table 5. Register 0 - Input port register bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol I7 I6 I5 I4 I3 I2 I1 I0

Table 6. Register 1 - Output port register bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol O7 O6 O5 O4 O3 O2 O1 O0

Default 00000000

Table 7. Register 2 - Polarity inversion register bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol N7 N6 N5 N4 N3 N2 N1 N0

Default 11110000

Table 8. Register 3 - Configuration register bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol C7 C6 C5 C4 C3 C2 C1 C0

Default 11111111

Product data sheet Rev. 7 — 10 December 2013 9 of 30

NXP Semiconductors

PCA9557

8-bit I

C-bus and SMBus I/O port with reset

7.4 Power-on reset

When power is applied to V

, an internal Power-On Reset (POR) holds the PCA9557 in

a reset condition until V

has reached V

POR

. At that point, the reset condition is released

and the PCA9557 registers and I

C-bus/SMBus state machine will initialize to their default

states. Thereafter, V

must be lowered below 0.2 V to reset the device.

7.5 RESET input

A reset can be accomplished by holding the RESET pin LOW for a minimum of t

w(rst)

. The

PCA9557 registers and SMBus/I

C-bus state machine will be held in their default state

until the RESET

input is once again HIGH. This input requires a pull-up resistor to V

no active connection is used.

8. Characteristics of the I

C-bus

The I

C-bus is for 2-way, 2-line communication between different ICs or modules. The two

lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stages

of a device. Data transfer may be initiated only when the bus is not busy.

8.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as control signals (see Figure 10

8.1.1 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line while the clock is HIGH is defined as the START condition (S). A

LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP

condition (P) (see Figure 11

Fig 10. Bit transfer

mba607

data line

stable;

data valid

change

of data

allowed

SDA

SCL

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30

PCA9557BSHP

Mfr. #:

Buy PCA9557BSHP

Manufacturer:

NXP Semiconductors

Description:

Interface - I/O Expanders 8-bit I2C-bus and SMBus I/O port with reset

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New from this manufacturer.

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PCA9557BSHP

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