PCA9557 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 10 December 2013 4 of 30
NXP Semiconductors
PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
On power-up or reset, all registers return to default values.
Fig 3. Simplified schematic of IO1 to IO7
V
DD
IO1 to IO7
output port
register data
configuration
register
DQ
CK Q
data from
shift register
write configuration
pulse
output port
register
DQ
CK
write pulse
polarity inversion
register
DQ
CK
data from
shift register
write polarity
pulse
input port
register
DQ
CK
read pulse
input port
register data
polarity inversion
register data
002aad278
FF
data from
shift register
FF
FF
FF
V
SS
ESD protection
diode
ESD protection
diode
PCA9557 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 10 December 2013 5 of 30
NXP Semiconductors
PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration for SO16 Fig 5. Pin configuration for TSSOP16
Fig 6. Pin configuration for HVQFN16
PCA9557D
SCL V
DD
SDA RESET
A0 IO7
A1 IO6
A2 IO5
IO0 IO4
IO1 IO3
V
SS
IO2
002aad272
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
IO7
IO6
IO5
IO4
IO3
IO2
SCL
SDA
A0
A1
A2
IO0
IO1
V
SS
PCA9557PW
002aad273
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
V
DD
RESET
002aad274
PCA9557BS
Transparent top view
IO0
IO4
A2 IO5
A1 IO6
A0 IO7
IO1
V
SS
IO2
IO3
SDA
SCL
V
DD
RESET
4 9
3 10
2 11
1 12
5
6
7
8
16
15
14
13
terminal 1
index area
Table 3. Pin description
Symbol Pin Description
SO16, TSSOP16 HVQFN16
SCL 1 15 serial clock line
SDA 2 16 serial data line
A0 3 1 address input 0
A1 4 2 address input 1
A2 5 3 address input 2
IO0 6 4 input/output 0 (open-drain)
IO1 7 5 input/output 1
PCA9557 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 10 December 2013 6 of 30
NXP Semiconductors
PCA9557
8-bit I
2
C-bus and SMBus I/O port with reset
[1] HVQFN16 package die supply ground is connected to both the V
SS
pin and the exposed center pad. The
V
SS
pin must be connected to the supply ground for proper device operation. For enhanced thermal,
electrical, and board-level performance, the exposed pad needs to be soldered to the board using a
corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias
need to be incorporated in the PCB in the thermal pad region.
6. System diagram
V
SS
86
[1]
supply ground
IO2 9 7 input/output 2
IO3 10 8 input/output 3
IO4 11 9 input/output 4
IO5 12 10 input/output 5
IO6 13 11 input/output 6
IO7 14 12 input/output 7
RESET
15 13 active LOW reset input
V
DD
16 14 supply voltage
Table 3. Pin description
…continued
Symbol Pin Description
SO16, TSSOP16 HVQFN16
Fig 7. System diagram
002aad276
Q7
1.1 kΩ
RESET
1.6 kΩ
SCL
1.6 kΩ
SDA
1.1 kΩ
A2
or
1.1 kΩ
A1
or
1.1 kΩ
A0
or
I
2
C-BUS/SMBus
INTERFACE
LOGIC
Q6
Q5
Q4
Q3
Q2
Q1
Q0
INPUT
PORT
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
POLARITY
INVERSION
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
CONFIG.
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
OUTPUT
PORT
1.1 kΩ
IO0
IO7
IO6
IO5
IO4
IO3
IO2
IO1

PCA9557BSHP

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Interface - I/O Expanders 8-bit I2C-bus and SMBus I/O port with reset
Lifecycle:
New from this manufacturer.
Delivery:
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