BR262CPP01GEVK Datasheet BR262CPP01GEVK | P4-P6

BelaSigna R262

www.onsemi.com

Table 2. ELECTRICAL CHARACTERISTICS (The typical parameters in Table 2 were measured at 20°C with a clean

3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified

for all process corners but not tested on every part.)

Parameter

Symbol Test Conditions / Notes Min Typ Max Unit Screened

DIGITAL MICROPHONE OUTPUT

DMIC input clock frequency

With preset 0 selected on

CLOCK_SEL (Note 3)

2.048 MHz

With preset 3 selected on

CLOCK_SEL (Note 3)

2.4 MHz

With preset 4 selected on

CLOCK_SEL (Note 3)

2.8 MHz

With preset 5 selected on

CLOCK_SEL (Note 3)

3.072 MHz

Clock duty cycle Any clock configuration 40 50 60 %

Input clock jitter Maximum allowed jitter on the

DMIC_CLK

10 ns

Clock to output transition time DMIC_OUT 10 20 50 ns

ANALOG OUTPUT STAGE

Signal Range

Vout

One single ended DAC used 0 2 Vpp

Two DACs used as one

differential output

0 4 Vpp

Attenuator gain tolerance −2 2 dB

Output impedance Rout

@ 12 dB output attenuation 19

kW l

@ 0 dB output attenuation 3

Channel cross coupling @ 1 kHz −50 dB

Analog Filter cut−off frequency

LPF Enabled (default) 13.0 13.5 kHz

LPF Disabled 25 26 kHz

Analog Filter passband flatness −1 1 dB

Analog filter stopband

attenuation

> 60 kHz 90 dB

Digital Filter cut−off frequency Fs/2 kHz

Digital Filter cut−off stopband

attenuation

80 dB

Total Harmonic Distortion +

Noise (Peak value)

THDN 63 65 dB

Dynamic Range DR 78 80 dB

Noise Floor 70 100

mV l

DIRECT DIGITAL OUTPUT (available only through custom configuration)

Supply voltage

VBATRCVR 1.8 3.3 3.63 V

Signal Range Vout

Differential Output @ 1 kHz 0 2*VBAT

RCVR

Vpp

Single ended Output @ 1 kHz 0 VBAT

RCVR

Vpp

Output Impedance Rout Load between

1 mA and 30 mA @ 0°C

2.5 10

Maximum Current 25 mA

Total Harmonic Distortion +

Noise (Peak value)

THDN 64 70 dB

3. Many other clock frequencies are available through custom configuration of the internal PLL and clocking subsystem. See later in this

document and in the BelaSigna R262 Communications and Configuration Guide for more information on custom mode usage.

BelaSigna R262

www.onsemi.com

Table 2. ELECTRICAL CHARACTERISTICS (continued) (The typical parameters in Table 2 were measured at 20°C with a clean

3.3 V supply voltage (unless noted differently). Parameters marked as screened are tested on each chip. Other parameters are qualified

for all process corners but not tested on every part.)

Parameter ScreenedUnitMaxTypMinTest Conditions / NotesSymbol

DIRECT DIGITAL OUTPUT (available only through custom configuration)

Dynamic Range

DR 80 86 dB

Noise Floor 50 75

mV l

LOW−SPEED A/D

Input voltage

Vin 0 2*VREG V

Sampling frequency For each LSAD channel 1.6 MCLK/28 4.8 kHz

Input impedance Rin 1

Offset error Input at VREG −10 10 LSB

Gain error Input to VSSA or 2*VREG −10 10 LSB

INL INL −4 4 LSB

DNL DNL −2 2 LSB

DIGITAL PADS (VDDO = 1.8 V)

Voltage level for Low input

VIL −0.3 0.4 V

Voltage level for High input VIH 1.30 1.98 V

Pull−up resistance 63 114 162

Pull−down resistance 87 153 205

Rise and Fall Time 20 pF load 2 3 5 ns

DIGITAL PADS (VDDO = 3.3 V)

Voltage level for Low input

VIL −0.3 0.8 V

Voltage level for High input VIH 1.8 3.6 V

Pull−up resistance 34 46 74

kW l

Pull−down resistance 29 56 86

kW l

Rise and Fall Time 20 pF load 1.0 1.5 2.0 ns

DIGITAL PADS (Common parameters)

Drive Strength

12 mA

ESD Immunity

HBM Human Body Model 2 kV

MM Machine Model 200 V

Latch−up Immunity 25°C, V < GNDO, V > VDDO 150 mA

CLOCKING CIRCUITRY

External clock frequency

EXT_CLK With preset 6 selected on

CLOCK_SEL (Note 3)

26 MHz

Internal clock frequency INT_CLK

With preset 7 selected on

CLOCK_SEL (Note 3)

Bypass Mode

5.2 MHz

With preset 7 selected on

CLOCK_SEL (Note 3)

Active Mode

48.2 MHz

Reference clock duty cycle 40 50 60 %

External Input clock jitter Maximum allowed jitter on

EXT_CLK

10 ns

C INTERFACE

Maximum speed

400 kbps

3. Many other clock frequencies are available through custom configuration of the internal PLL and clocking subsystem. See later in this

document and in the BelaSigna R262 Communications and Configuration Guide for more information on custom mode usage.

BelaSigna R262

www.onsemi.com

Table 3. PIN CONNECTIONS

Pin Index Pin Name Description A/D/P I/O Active Pull

G1 MIC0 First microphone input A I

E1 MIC2 Second microphone input A I

E3 AI3/VMIC/LOUT0 Direct audio input / microphone bias /

line−out preamp 0

A I/O

E7 A_OUT1 Audio output 1 A O

G7 CAP0 Charge pump capacitor connection A I/O

F8 CAP1 Charge pump capacitor connection A I/O

A1 DEBUG_RX RS232 debug port serial input D I L U

B2 DEBUG_TX RS232 debug port serial output D O L

F2 RESERVED Reserved

A3 EXT_CLK External clock input D I U

A7 SPI_CLK/CLOCK_SEL SPI clock / Clock selection D/A O/I L/−

A9 SPI_CS/BOOT_SEL SPI chip select / Booting method selection D/A O/I

B8 SPI_SERO/CHAN_SEL SPI serial output / Channel selection D/A O/I

C9 SPI_SERI/ALPHA_SEL SPI serial input / Mixing ratio selection D/A I/I U/−

C7 DMIC_OUT Digital microphone output D O

C3 I2C_SDA I

C data D IO L U

C1 I2C_SCL I

C clock D IO L U

F6 VBAT Power supply P I

G9 VBATRCVR Output driver power supply P I

G5 VDDA Analog supply voltage P O

B6 VDDD Digital power supply P O

B4 VDDO Digital I/O power supply P I

G3 VREG Analog supply voltage P O

F4 VSSA Analog ground P I

A5 VSSD Digital ground P I

E9 VSSRCVR Output driver ground P I

A: Analog pin

D: Digital pin

P: Power pin

I: Input

O: Output

IO: Bi−directional

I/O & O/IL: Input or Output depending on the function being used

L: Active Low

H: Active High

U: Pulled up internally

D: Pulled down internally

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

BR262CPP01GEVK

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