Rev 1 - November 2008
©2008 Semtech Corp.
SX1781
www.semtech.com
Page 10
PLL Frequency Synthesizer with integrated VCO
ADVANCED COMMUNICATIONS & SENSING FINAL
DATASHEET
10. Registers Description
The memory map of the registers is shown below.
Table 10 Memory Map of Registers
10.1. RegNDivLsb Register
This register is a read/write register. It configures the least significant 8-bits of Ndiv, the feedback divider ratio of the PLL.
As writing RegNDivLsb triggers the calibration of the VCO, the user should first update RegNdivMsb, then configure
RegNdivLsb if both need to be updated in a frequency hop. Doing this avoids wrong calibration sequences and extended
lock times.
10.2. RegNDivMsb Register
This register is a read/write register. Bits [1:0] configure the two most significant bits of Ndiv, the feedback divider ratio of
the PLL.
10.3. RegRDiv Register
This register is a read/write register. The five least significant bits configure the division factor of the Rdiv prescaler of the
PLL.
10.4. RegGenCtrl Register
This register is a read/write register to configure the output and calibration modes.
Internal Address Register Address
byte
Register
Name
Default
value
Read
Write
D7 D6 D5 D4 D3 D2 D1 D0
NDiv[7:0]
0x00 RegNDivLsb 0x00 R/W
NDiv[9:8]
0x01 RegNDivMsb 0x00 R/W
RDiv[5:0]
0x02 RegRDiv 0x00 R/W
Squelch Cal_
mode
Outp_config
[1:0]
0x03 RegGenCtrl 0x00 R/W
Register Bits Description
b[3] RF out upon Lock Detection:
0 : The RF output is enabled only when the PLL is locked (Default)
1 : The RF output is enabled whatever the Lock detector state.
b[2] Calibration mode
0 : Writing to RegNDivLsb triggers calibration (Default)
1 : Writing to RegRDiv or RegNDivLsb triggers calibration
b[1:0] Output Buffer Current
00 : Output current is 3.5 mA (Default)
01 : Output current is 5 mA
10 : Output current is 7.5 mA
11 : Output current is 11 mA
