Rev 1 - November 2008
©2008 Semtech Corp.
SX1781
www.semtech.com
Page 6
PLL Frequency Synthesizer with integrated VCO
ADVANCED COMMUNICATIONS & SENSING FINAL
DATASHEET
5. RF Characteristics
Table 7 RF Characteristics
Notes:
1: Value of Rdiv is as programmed into the input divider
2: PFD update frequency should be maintained as close to 500 kHz as possible for optimum phase noise performance. Other divider values can be
programmed to reduce the PFD update rate, but this is not recommended due to the internal loop bandwidth being preset @ 50kHz.
3: No SPI access should be performed during tpup or thop, while the VCO is being calibrated.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
CLK Input Reference Frequency
F
REF
External Reference 0.5 - 26 MHz
PFD Update Frequency (1)
fφ fφ= F
REF
/(Rdiv+1) 500
(2)
- - kHz
VCO Center Frequency Range
F
CEN
- 2400 - 2800 MHz
PLL Output Frequency Range
F
OUT
- 1200 - 1400 MHz
Phase Noise
at 10 kHz offset -
Fout=1290 MHz
fφ = 500 kHz
F
REF
=26 MHz
- -85 -75 dBc/Hz
Integrated Jitter - 100Hz to 100kHz - 2.4 4 ps
Loop Bandwidth - Closed Loop - 50 - kHz
Harmonic Suppression H2 Second Harmonic - -26 -20 dBc
Maximum RFOUT Power Level Pout
Single output into 50 ohm - -1 - dBm
Differential outputs
combined in a balun
- +5 - dBm
Output Power Tolerance ∆Pout - -3 - +3 dB
Output Reference Spurs - Offset = 500 kHz - -67 - dBc
Output Spurs - All other spurs - -67 - dBc
Hopping Time (3)
across entire tuning range thop
To +/- 1 ppm precision - - 500 µs
To LD pin rising edge - - 350 µs
Power Up Request from
SLEEPB rising (3)
(input reference settled)
tpup
To +/- 1 ppm precision - - 750 µs
To LD pin rising edge - - 625 µs
Power Down Request to
Synthesizer off Time
t
pdn
SLEEPB falling - - 100 ns
