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SX1781IMLTRT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
Rev 1 - November 2008
©2008 Semtech Corp.
SX1781
www.semtech.com
Page 7
PLL Frequency Synthesizer with integrated VCO
ADVANCED COMMUNICATIONS & SENSING FINAL
DATASHEET
6. Serial Interface: Slave SPI
The device is configured with a serial microprocessor bus. Figure 1 and Figure 2 show the timing diagrams of write and
read accesses. The serial interface is SPI compatible with a 16-bit word. The serial interface clock (SCK) is not required to
run between accesses (i.e., when CSB = 1).
6.1. Read Register
To read the value of a configuration register the timing diagram below should be carefully followed by the uC.
Figure 1. Read Register Timing
When reading more than one register successively, it is not compulsory to toggle CSB back high between two cycles. The
bytes are alternatively considered as address and value.
MOSI: Master latches the address bit value on SCK falling edge and Slave samples the data on rising edge of SCK.
MISO: Slave latches the register bit value on falling edge of SCK and Master samples the value on the next rising edge.
Table 8 SPI Read Timings
Parameter Symbol Minimum Typical Maximum Unit
SPI Clock Frequency Fsck - - 20 MHz
Setup MOSI valid to SCK
rising edge
tsdata 4 - - ns
Setup CSB
falling edge
to SCK
rising edge
tscsb 14 - - ns
Delay SCK
falling edge
to MISO valid td1 - - 25 ns
Delay CS
Brising edge
to MISO high-Z td2 - 25 - ns
SCK Low time tcl 25 - - ns
SCK High time tch 25 - - ns
Hold MOSI valid after SCK
rising edge
thdata 6 - - ns
Hold CSB Low after SCK
rising edge
thcsb 6 - - ns
Time between two accesses (CSB
rising edge
to CSB
falling edge
) tp 25 - - ns
Rev 1 - November 2008
©2008 Semtech Corp.
SX1781
www.semtech.com
Page 8
PLL Frequency Synthesizer with integrated VCO
ADVANCED COMMUNICATIONS & SENSING FINAL
DATASHEET
6.2. Write Register
To write a value into a configuration register the timing diagram below should be carefully followed by the uC.
Figure 2. SPI Write Timing
Note that when writing more than one registers successively, it is not compulsory to toggle CSB back high between two
cycles. The bytes are alternatively considered as address and value. In this instance, all new values will become effective
on the rising edge of CSB.
The Master latches the data on SCK falling edge and Slave samples the data on rising edge of SCK.
MISO pin reflects the previous Write access. For the Write access, MISO stays low. MISO pin is tri-stated when CSB is
high and when the device is in Sleep mode (SLEEPB is low).
Table 9 SPI Write Timings
Parameter Symbol Minimum Typical Maximum Unit
SPI Clock Frequency Fsck - - 20 MHz
Setup MOSI valid to SCK
rising edge
tsdata 4 - - ns
Setup CSB
falling edge
to SCK
rising edge
tscsb 14 - - ns
Delay SCK
falling edge
to MISO valid td1 - - 25 ns
Delay CS
Brising edge
to MISO high-Z td2 - 25 - ns
SCK Low time tcl 25 - - ns
SCK High time tch 25 - - ns
Hold MOSI valid after SCK
rising edge
thdata 6 - - ns
Hold CSB Low after SCK
rising edge
thcsb 6 - - ns
Time between two accesses (CSB
rising edge
to CSB
falling edge
) tp 25 - - ns
Rev 1 - November 2008
©2008 Semtech Corp.
SX1781
www.semtech.com
Page 9
PLL Frequency Synthesizer with integrated VCO
ADVANCED COMMUNICATIONS & SENSING FINAL
DATASHEET
7. Input Reference Signal
The input reference signal of the PLL enters pin 2 CLK. To meet the phase noise performance of the synthesizer, the phase
noise of the clock source (denoted PN
CLK
) at a 10 kHz distance of the carrier should be such that:
PN
CLK
< -160 + 20.log(Rdiv+1) dBc/Hz @ 10 kHz
A TCXO is an appropriate signal source at CLK input.
Two different connection schemes are possible, depending of the type of source :
CMOS output device : the source should be directly DC connected to the CLK input, and its levels should be compliant
with the specification of Table 6.
Sine or clipped sine output: AC coupling, through a 560pF capacitor, should be used. In this case a minimum swing of
0.5 volts triggers the divider input (see Table 6).
8. RF Frequency Setting
The RF Output frequency is calculated from the following formula:
Where
Ndiv is controlled in a 10-bit register and Rdiv in a 6-bit register to be programmed through the SPI interface.
Fref is the input reference frequency, of the signal applied on pin 2 (CLK). Note that the recommended value of
is 500 kHz, which allows for a minimum frequency step of 250 kHz.
9. Lock Detector and Squelch
A lock detection signal is mapped to pin 16 LD. It can be used as an interrupt request signal to the external world. This
signal can also be used to internally shut down the output buffers until the PLL gets locked. This squelch function can be
inhibited by setting bit 3 at address 3 to “1” (default = “0”, squelch active).
+
+
=
2
4800
*
1
Ndiv
Rdiv
F
Fout
ref
1+Rdiv
Fref
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

SX1781IMLTRT

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Phase Locked Loops - PLL PLL FREQ SYNTH WITH VCO
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