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STA016T
Description :
This register must contain a MDIV value that enables
the system PLL to generate a frequency of 42.5 MHz
for the SYSCK.See table 4.
Default value at soft reset assume :
– external crystal provide a CRYCK running at
14.31818 MHz
3.3 I2Sout_CONFIGURATION registers
description
OUTPUT_CONF
:
Address : 0x66 (102)
Type : RW - DEC
Software Reset : 0
Description :
If set to 1 enable the configurability of the PCM-
BLOCK Output thanks to following registers, else dis-
able this configurability and take embedded default
configuration for PCM-BLOCK registers.
Note that this embedded default configuration can be
retrieved by user thanks to following setting :
– PCM_DIV = 3;
–PCM_CONF = 0;
– PCM_CROSS = 0;
PCM_DIV :
Address : 0x67 (103)
Type : RW - DEC
Software Reset : 0
Description :
If OUTPUT_CONF == 1, configure the divider to gen-
erate the bit clock of the I2Sout interface, called
BCK0, from PCMCK. according the following relation
: BCKO = PCMCK / 2 * (PCM_DIV+1)
PCM_CONF
:
Address : 0x68 (104)
Type : RW - DEC
Software Reset : 0
Description :
If OUTPUT_CONF == 1, configure the I2Sout inter-
face according following table.
PCM_CROSS
:
Address : 0x69 (105)
Type : RW - DEC
Software Reset : 0
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
0 0 DV5 DV4 DV3 DV2 DV1 DV0
b7 b6 b5 b4 b3 b2 b1 b0
0 CO6 CO5 CO4 CO3 CO2 CO1 CO0
Bit
fields
Comment
CO[1:0] 0 : 16 bits mode (16 slots transmitted).
1 : 18 bits mode (18 slots transmitted).
2 : 20 bits mode (20 slots transmitted).
3 : 24 bits mode (24 slots transmitted).
CO2 Polarity of BCKO :
0 : data are sent on the falling edge & stable
on the rising).
1 : (data are sent on the rising edge & stable
on the falling).
CO3 0 : I2S format is selected
1 : other format is selected
CO4 Polarity of LRCKO :
0 : low->right, high->left).
1 : low->left, high->right so compliant to I2S
format ).
CO5 0 : data are in the last BCKO cycles of
LRCKO (right aligned data).
1 : data are in the first BCKO cycles of
LRCKO (left aligned data).
CO6 0 : the transmission is LS bit first.
1 : the transmission is MS bit first.
b7 b6 b5 b4 b3 b2 b1 b0
000000CR1CR0
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