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STA016T13TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45
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I/O CELL DESCRIPTION
1) TTL Tristate Output Pad Buffer
, 3V capable 4mA, with Slew Rate Control
Pin numbers: 4, 18, 20, 21, 22, 25, 54, 56, 59
2) TTL Schmitt Trigger Bidir Pad Buffer
, 3V capable, 4mA, with Slew Rate Control
Pin numbers: 1, 2, 3, 7, 8, 9, 19
3) TTL Schmitt Trigger Inpud Pad Buffer
, 3V capable / Pin numbers:17, 60, 63
4) TTL Inpud Pad Buffer,
3V capable with Pull-Up / Pin numbers:15, 16
5) TTL Schmitt Trigger Bidir Pad Buffer
, with Pull-up, 4mA, with slew rate control / 3V capable
Pin numbers: 26, 27, 28, 31, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 51, 64
6) TTL Input Pad Buffer,
3V capable, with pull down / Pin numbers: 12, 13, 14, 55
INPUT PIN MAX LOAD
Z 100pF
INPUT PIN CAPACITANCE
OUTPUT
PIN
MAX
LOAD
IO TBD IO 100pF
INPUT PIN CAPACITANCE
ATBD
INPUT PIN CAPACITANCE
ATBD
INPUT PIN CAPACITANCE
OUTPUT
PIN
MAX
LOAD
IO TBD IO 100pF
INPUT PIN CAPACITANCE
ATBD
EN
A
D98AU904
Z
EN
A
D98AU905
ZI
IO
A
D98AU906
Z
A
D98AU907
Z
EN
A
D00AU1150
ZI
IO
A
D00AU1222
Z
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STA016T
4 COMMAND PROTOCOL CONFIGURATION
General Information About The Command Protocol
I2C protocol :
CD_module & mmdsp are using an I2C protocol to communicate : CD_module is master of the I2C protocol,
and can access (in read and write mode) host registers of the sta016 to write commands to the mmdsp and to
read request from the mmdsp. It must use following I2C syntax :
device_address, host_register_number, host_register_value
where :
for a write acces, device_address is 0x86.
for a read acces, device_address is 0x87.
Writing a command to mmdsp :
CD_module write its command inside dedicated host registers (mainly H64 to H69), then it must signals the writ-
ing of this command to mmdsp by sending the interrupt IT_CMD to the core of mmdsp.
Note that IT_CMD is generated by cd_module threw a falling edge on the input line number 0 of the sta016 (the
INTLINE[0] pin).
Reading a request from mmdsp :
MMDSP write its request inside dedicated host registers (mainly H70 to H78 and H134 to H169), then it signals
to cd_module that it must read a request by sending the interrupt IT_REQ.
Note that IT_REQ interrupt is generated by mmdsp on the IRQB pin of sta016.
Note also that once it has finished to read the message, cd_module must always acknowledge it by reading
H10.
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Figure 4. Block diagram for running the CD application.
power on
cd
inserted ?
no
wait IT_REQ
with 35 in H70
start cd-rom application:
write 0 in H85, then 1 in H86
send play_music command :
write 112 in H64
send IT_CMD
wait IT_REQ
with 112 in H70
any
command?
cd
ejected?
run other
application?
send pause command :
write 2 in H64
send IT_CMD
run the other
application
no
yes
yes
return
to cd?
no
yes
send other command :
write in H64
send IT_CMD
Hxx: host register
number xx
write 1 in SOFT_RESET
write 0 in CK_CMD
Obsolete Product(s) - Obsolete Product(s)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45

STA016T13TR

Mfr. #:
Buy STA016T13TR
Manufacturer:
STMicroelectronics
Description:
IC DECODER AUDIO 2.5 64TQFP
Lifecycle:
New from this manufacturer.
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