LTC3548-2
13
35482fb
Figure 3. LTC3548-2 Typical Application
APPLICATIONS INFORMATION
The output voltage, V
OUT2
, can now be programmed by
choosing the values of R1 and R2. To maintain high effi -
ciency, the current in these resistors should be kept small.
Choosing 2μA with the 0.6V feedback voltage makes R1
approximately 280k. A close standard 1% resistor is 280k,
and R2 is then 887k.
The POR pin is a common drain output and requires a pull-
up resistor. A 100k resistor is used for adequate speed.
Figure 3 shows the complete schematic for this design
example.
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3548-2. These items are also illustrated graphically
in the layout diagram of Figure 4. Check the following in
your layout:
1. Does the capacitor C
IN
connect to the power V
IN
(Pin 3)
and GND (Exposed Pad) as close as possible? This
capacitor provides the AC current to the internal power
MOSFETs and their drivers.
2. Are the C
OUT
and L1 closely connected? The (–) plate of
C
OUT
returns current to GND and the (–) plate of C
IN
.
3. The resistor divider, R1 and R2, must be connected
between the (+) plate of C
OUT
and a ground sense line
terminated near GND (Exposed Pad). The feedback
signals V
OUT1
, V
FB2
should be routed away from noisy
components and traces, such as the SW line (Pins 4
and 7), and its trace should be minimized.
4. Keep sensitive components away from the SW pins. The
input capacitor C
IN
and the resistors R1 to R2 should be
routed away from the SW traces and the inductors.
5. A ground plane is preferred, but if not available, keep the
signal and power grounds segregated with small signal
components returning to the GND pin at one point and
should not share the high current path of C
IN
or C
OUT
.
6. Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected
to V
IN
or GND.
Figure 4. LTC3548-2 Layout Diagram
(See Board Layout Checklist)
RUN2 V
IN
V
IN
2.5V* TO 5.5V
V
OUT2
2.5V*
400mA
V
OUT1
1.8V
800mA
RUN1
POR
SW1
V
OUT1
GND
V
FB2
SW2
MODE/SYNC
LTC3548-2
C1
10μF
R5
100k
POWER-ON
RESET
C5 68pF
L1
2.2μH
L2
4.7μH
R2
887k
C3
4.7μF
C2
10μF
35482 F03
C1, C2, C3: TAIYO YUDEN JMK212BJ106MG
C3: TAIYO YUDEN JMK212BJ475MG
L1: MURATA LQH32CN2R2M11
L2: MURATA LQH32CN4R7M23
*V
OUT
CONNECTED TO V
IN
FOR V
IN
b 2.8V (DROPOUT)
R1
280k
RUN2 V
IN
V
IN
V
OUT2
V
OUT1
RUN1
POR
SW1
V
OUT1
GND
V
FB2
SW2
MODE/SYNC
LTC3548-2
C
IN
C5
L1
L2
R2
R1
C
OUT2
C
OUT1
35482 F04
BOLD LINES INDICATE
HIGH CURRENT PATHS
