6©2016 Integrated Device Technology, Inc Revision A March 30, 2016
830154I-08 Data Sheet
Table 5B. AC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized up to F
OUT
150MHz.
NOTE 1: Measured from the V
DD
/2 of the input to V
DD
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DD
/2.
Table 5C. AC Characteristics, V
DD
= 1.8V ± 0.15V, T
A
= -40°C to 85°C
For NOTES, see Table 5B above.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 160 MHz
tp
LH
Propagation Delay
(low to high transition); NOTE 1
0.8 1.7 ns
tp
HL
Propagation Delay
(high to low transition); NOTE 1
0.8 1.7 ns
t
PLZ,
t
PHZ
Disable Time
(active to high-impedance)
10 ns
t
PZL,
t
PZH
Enable Time
(high-impedance to disable)
10 ns
tsk(o) Output Skew; NOTE 2, 3 250 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
25MHz, Integration Range:
12kHz - 5MHz
0.076 ps
t
R
/ t
F
Output Rise/Fall Time 10% to 90% 0.35 1.2 ns
odc Output Duty Cycle 48 52 %
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 160 MHz
tp
LH
Propagation Delay
(low to high transition); NOTE 1
1.1 2.1 ns
tp
HL
Propagation Delay
(high to low transition); NOTE 1
1.1 2.1 ns
t
PLZ,
t
PHZ
Disable Time
(active to high-impedance)
10 ns
t
PZL,
t
PZH
Enable Time
(high-impedance to disable)
10 ns
tsk(o) Output Skew; NOTE 2, 3 250 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
25MHz, Integration Range:
12kHz - 5MHz
0.193 ps
t
R
/ t
F
Output Rise/Fall Time 0.63V to 1.17V 0.12 0.6 ns
odc Output Duty Cycle 47 53 %
