7©2016 Integrated Device Technology, Inc Revision A March 30, 2016
830154I-08 Data Sheet
Table 5D. AC Characteristics, V
DD
= 1.5V ± 0.1V, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized up to F
OUT
150MHz.
NOTE 1: Measured from the V
DD
/2 of the input to V
DD
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DD
/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V
DD
/2.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
OUT
Output Frequency 160 MHz
tp
LH
Propagation Delay
(low to high transition); NOTE 1
1.5 2.7 ns
tp
HL
Propagation Delay
(high to low transition); NOTE 1
1.5 2.7 ns
t
PLZ,
t
PHZ
Disable Time
(active to high-impedance)
10 ns
t
PZL,
t
PZH
Enable Time
(high-impedance to disable)
10 ns
tsk(o) Output Skew; NOTE 2, 3 250 ps
tsk(pp) Part-to-Part Skew; NOTE 2, 4 800 ps
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
25MHz, Integration Range:
12kHz - 5MHz
0.266 ps
t
R
/ t
F
Output Rise/Fall Time 0.525V to 0.975V 0.12 0.6 ns
odc Output Duty Cycle 47 53 %
8©2016 Integrated Device Technology, Inc Revision A March 30, 2016
830154I-08 Data Sheet
Additive Phase Jitter (1.5V Output)
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a Phase
noise plot and is most often the specified plot in many applications.
Phase noise is defined as the ratio of the noise power present in a
1Hz band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
(dBm) or a ratio of the power in the 1Hz band to the power in the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency
domain, we get a better understanding of its effects on the desired
application over the entire time record of the signal. It is
mathematically possible to calculate an expected bit error rate given
a phase noise plot.
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator "IFR2042 10kHz – 56.4GHz Low Noise Signal
Generator as external input to an Agilent 8133A 3GHz Pulse
Generator".
Additive Phase Jitter @ 25MHz
12kHz to 5MHz = 0.266ps (typical)
SSB Phase Noise dBc/Hz
Offset from Carrier Frequency (Hz)
9©2016 Integrated Device Technology, Inc Revision A March 30, 2016
830154I-08 Data Sheet
Parameter Measurement Information
3.3V Output Load AC Test Circuit
1.8V Output Load AC Test Circuit
Output Skew
2.5V Output Load AC Test Circuit
1.5V Output Load AC Test Circuit
Part-to-Part Skew
SCOPE
Qx
GND
V
DD
1.65V±5%
-1.65V±5%
SCOPE
Qx
GND
V
DD
0.9V±0.075V
-0.9V±0.075V
t
sk(o)
V
DD
2
V
DD
2
Qx
Qy
SCOPE
Qx
GND
V
DD
1.25V±5%
-1.25V±5%
SCOPE
Qx
GND
V
DD
0.75V±0.05V
-0.75V±0.05V
Qx
tsk(pp)
V
DD
2
V
DD
2
Part 1
Part 2
Qy

830154AMI-08LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer ICS
Lifecycle:
New from this manufacturer.
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