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LC717A30UJ-AH

P1-P3P4-P6P7-P9P10-P12P13-P14
LC717A30UJ
www.onsemi.com
10
POR
(LSI internal signal)
Release
t
POR
V
DD
Reset
t
VDD
INTOUT
V
POROP
Cin0 to Cin7,
CMAdd0,
CMAdd4,
Cref, CrefAdd,
CdrvBa
r
VALID
t
POROP
Reset Release
t
POR
VALID
Hi-Z
POR
(LSI internal signal)
Release
t
NRST
V
DD
Reset
INTOUT
Cin0 to 7,
CMAdd0,
CMAdd4,
Cref, CrefAdd,
CdrvBa
r
VALID
Reset Release
t
POR
VALID
nRST
Reset Reset
t
POR
t
NRST
FUNCTIONAL DESCRIPTION
Power-on Reset (POR)
When power is turned on, power-on reset is enabled, it is
released after power-on reset time, t
POR
. Power-on reset
operation condition; Power supply rise rate t
VDD
must be at
least 1.0 V/ms.
.
Since INTOUT pin changes from “High” to “Low” at the same
time as reset release, it is possible to verify the timing of release
of reset externally. During power-on reset, Cin0 to Cin7,
CMAdd0, CMAdd4, Cref, CrefAdd, and CdrvBar are unknown.
Figure 6. Power-on Sequence by the Power-on Reset
External Reset (nRST)
Reset State nRST = “Low”. Pins Cin0 to Cin7, CMAdd0,
CMAdd4, Cref, CrefAdd and CdrvBar, are “Hi-Z” during reset
state. The reset state is released after t
POR
.
Since INTOUT pin changes from “High” to “Low” at the same
time as the released of reset, it is possible to verify the timing of
release of reset externally.
Figure 7. Power-on Sequence by the External Reset
Unknown Unknown
Unknown
Unknown
100%
0%
Hi-Z
Unknown Unknown
100%
0%
LC717A30UJ
www.onsemi.com
11
SDA
SCL
START
condition
t
HD;STA
t
LOW
t
HIGH
t
r
Repeated START
condition
STOP
condition
t
f
10%
90%
t
HD;DTA
t
SU;DTA
10%
90%
t
SU;STA
t
HD;STA
t
SU;STO
t
BUF
START
condition
I
2
C Data Timing
Figure 8. I
2
C Data Timing
I
2
C Communication Formats
Write Format
When using the Write format of I
2
C the data can be written
into sequentially incremented addresses.
Figure 9. I
2
C Write Format
Read Format
When using the Read format of I
2
C the data can be read from
sequentially incremented addresses.
Figure 10. I
2
C Read Format
I
2
C Slave Address
SA0 pin is used to select the slave address
Table 1. I
2
C Slave Address
SA0 pin input 7 bit slave address Binary notation 8 bit slave address
Low 0x16 00101100b (Write) 0x2C
00101101b (Read) 0x2D
High 0x17 00101110b (Write) 0x2E
00101111b (Read) 0x2F
START Slave address Write=L ACK Register address (N) ACK Data written to register address (N) ACK Data written to register address (N+1) ACK STOP
Slave Slave Slave Slave
START Slave address Write=L ACK Register address (N) ACK
Slave Slave
Slave address Read=H ACK Data read from register address (N) ACK Data read from register address (N+1) ACK Data read from register address (N+2) NACK STOP
Slave Master Master Master
RE-
START
LC717A30UJ
www.onsemi.com
12
nCS
SO
SCK
SI
SPI Data Timing (Mode 0 / Mode 3)
Figure 11. SPI Data Timing
SPI write Format (Example of Mode 0)
When using the SPI Write format the data can be written into
sequentially incremented addresses with preserving nCS = ‟L”.
Figure 12. SPI Write Format
SPI Read Format
When using the SPI Read format the data can be read from
sequentially incremented addresses with preserving nCS = ‟L”.
Figure 13. SPI Read Format
90%
t
HD;SO
t
SU;SI
VALID
t
r
t
HD;SI
t
SU;NCS
t
HIGH
t
LOW
t
f
t
CPH
t
HD;NCS
t
HD;SCK
t
CLZ
t
CHZ
VALID
t
V
Hi-Z
50%
50%
10%
50%
50%
Hi-Z
t
SU;SCK
nCS
SCK
SI
SO
Hi-Z
Write=L
Register address (N) Data written to register address (N) Data written to register address (N+1)
76543210765432107
76543210
nCS
SCK
SI
SO
Hi-Z
Read=H
Register address (N)
Data read from register address (N) Data read from register address (N+1)
P1-P3P4-P6P7-P9P10-P12P13-P14

LC717A30UJ-AH

Mfr. #:
Buy LC717A30UJ-AH
Manufacturer:
ON Semiconductor
Description:
Capacitive Touch Sensors Digital Converter for Touch Sensors
Lifecycle:
New from this manufacturer.
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