LC717A30UJ
www.onsemi.com
9
Continued from the previous page.
Note 12 : Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.
Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
13 : Apply to Cdrv, CdrvBar, SO, INTOUT.
14 : Apply to SCL/SCK, SDA/SI, SA0, nCS, nRST, IFSEL.
15 : Apply to Cdrv, CdrvBar, SDA, SO.
16 : Sensor pins (Cin0 to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd) are open condition.
17 : Apply to Cin0 to Cin7, CMAdd0, CMAdd4, Cref, CrefAdd.
ELECTRICAL CHARACTERICALS (CONTINUED) at V
DD
= 2.6 to 5.5 V, V
SS
= 0 V, T
A
= 40 to + 105°C, (Note 12)
Unless otherwise specified, the Cdrv drive frequency is f
CDRV
= 121 kHz.
Parameter Condition Symbol Min Typ Max Unit
I
2
C Compatible Bus Interface Timing
SCL Clock Frequency SCL
f
SCL
400 kHz
START Condition Hold Time SCL, SDA
t
HD; STA
0.6 μs
SCL Clock Low Period SCL
t
LOW
1.3 μs
SCL Clock High Period SCL
t
HIGH
0.6 μs
Repeated START Condition Setup Time SCL, SDA
t
SU; STA
0.6 μs
Data Hold Time SCL, SDA
t
HD; DAT
0 0.9 μs
Data Setup Time SCL, SDA
t
SU; DAT
0.5 μs
SDA, SCL Rise/Fall Time SCL, SDA
t
r
/t
f
0.3 μs
STOP Condition Setup Time SCL, SDA
t
SU; STO
0.6 μs
STOP-to-START Bus Release Time SCL, SDA
t
BUF
2.5 μs
SPI Interface Timing
SCK Clock Frequency SCK
f
SCK
5.0 MHz
SCK Clock Low Time SCK
t
LOW
100 ns
SCK Clock High Time SCK
t
HIGH
100 ns
Input Signal Rise/Fall Time nCS, SCK, SI
t
r
/t
f
300 ns
nCS Setup Time nCS, SCK
t
SU; NCS
200 ns
SCK Clock Setup Time nCS, SCK
t
SU; SCK
100 ns
Data Setup Time SCK, SI
t
SU; SI
100 ns
Data Hold Time SCK, SI
t
HD; SI
100 ns
nCS Hold Time nCS, SCK
t
HD; NCS
200 ns
SCK Clock Hold Time nCS, SCK
t
HD;SCK
700 ns
nCS Standby Pulse Width nCS
t
CPH
300 ns
Output High Impedance Time from nCS nCS, SO
t
CHZ
100 ns
Output Data Determination Time SCK, SO
t
V
100 ns
Output Data Hold Time SCK, SO
t
HD; SO
0 ns
Output Low Impedance Time from SCK
Clock
SCK, SO
t
CLZ
100 ns